Frequency presetting and phase error detection technique for fast-locking phase-locked loop

doi:10.1016/j.mejo.2014.01.003

Microelectronics Journal

Volume 45, Issue 4, April 2014, Pages 375-381

https://doi.org/10.1016/j.mejo.2014.01.003 Get rights and content

Abstract

A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35 μm CMOS process, with a supply voltage of 3.3 V.

Introduction

The phase-locked loop (PLL) architecture is widely used in clock generators in high performance microprocessors and high-speed digital communication systems. The optimization of PLL performance has some limitations. To have the optimal jitter performance for a specified PLL, the loop bandwidth should be carefully chosen according to the requirements of the applications. In the telecommunications system, such as in the switch between the communication channels, a fast response of PLL is required, particularly for frequency synthesis applications. Fast PLL can also help in reducing the power-up latency of the system and in saving energy for longer battery life in mobile products. To reduce the settling time, a wide loop bandwidth of a PLL would be needed. However, with wide bandwidth, the output phase jitter increases due to external noise. There is a trade-off between the phase jitter and settling time [1], [2], [3], [4], [5].

In this work, a frequency-to-voltage converter (FVC) is used to speed up the frequency acquisition time of the PLL [5]. The reference clock and divided voltage-controlled oscillator (VCO) clock is converted to voltage by FVC. The voltage difference is able to force the control voltage of the VCO to have a frequency close to the reference clock. However, because the phase error still occurs between the reference clock and the divided VCO clock, the phase error detector is able to afford a wider loop bandwidth for quick reduction of the phase error. The combination of both processes leads to a short locking time. The proposed PLL also avoids the trade-off between phase jitter and settling time. This paper is organized as follows. In Section 2, the architecture of the proposed circuit is introduced. Section 3 presents the circuit realization of the proposed PLL, which incorporates the fast-locking technique. Section 4 shows the measurement results. Finally, Section 5 concludes this paper.

Section snippets

Architecture of the proposed circuit

A linear model representing the charge pump PLL in the locked state is presented in Fig. 1. The closed-loop transfer function with a first-order low-pass filter can be expressed as $H (s) = \frac{ϕ_{out} (s)}{ϕ_{in} (s)} = M \frac{2 ς (s / ω_{n}) + 1}{{(s / ω_{n})}^{2} + 2 ς (s / ω_{n}) + 1}$ This equation is in a standard form of a first-order low-pass system with the damping factor (ζ) and natural frequency (ω_n) defined as follows: $ς = \frac{R_{S}}{2} \sqrt{\frac{I_{P} K_{VCO} C_{S}}{M}}$ $ω_{n} = \sqrt{\frac{I_{P} K_{VCO}}{M C_{S}}}$ where I_P is the charge pump current, K_VCO is the gain of VCO, and M is the divider ratio.

From Eq. (3),

Frequency presetting circuit

Fig. 3 shows the block diagram of the frequency presetting circuit, which consists of two frequency-to-voltage converters (FVC) [5], two D-type flip-flops (DFFs), an inverter and a comparator (Comp). The frequency of fvco and fclk are transferred into voltage levels (Vvco and Vclk) by the FVC. The output of the frequency presetting circuit, “freq”, is low at the beginning. After the reset of PLL, the frequency of the fvco is higher than the frequency of the fclk because the voltage of VC2 is

Measurement results

The frequency presetting and phase error detection technique for the fast-locking phase-locked loop is implemented in the 0.35 μm CMOS process. The microphotograph of the fabricated proposed circuit is shown in Fig. 13. The active area is 0.18 mm2. Fig. 14 shows the output signal spectrum of 828 MHz with a reference frequency of 46 MHz. The reference spurs are –21 dBc. The measured jitter histogram is shown in Fig. 15. The peak-to-peak jitter and rms jitter are 48.9 ps and 5.9 ps, respectively, at 828

Conclusion

The frequency presetting and phase error detection technique for the fast-locking phase-locked loop provides a means of improving the settling time. The settling time is improved by 86%. The proposed circuit is fabricated in a 0.35 μm CMOS process. The peak-to-peak jitter and rms jitter are 48.9 ps and 5.9 ps, respectively, at 828 MHz.

Acknowledgements

The authors would like to thank the National Science Council of Taiwan for the financial support under Grant no. NSC97-2218-E-182-001 and the National Chip Implementation Center (CIC) of Taiwan for fabricating this chip.

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Citation Excerpt :
The most commonplace approach to speed up the PLL is increasing the BW, however there is an optimum BW which guarantees best output phase noise performance [4]. In the BW switching approach [5–8] the BW is manifold during the transient time of frequency switching (fast locking mode) and returned to normal BW after lock condition is satisfied (normal mode). Fast locking mode lasts for a short time and during this time, the output frequency of PLL does not have the right value and cannot be used.
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