Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability

Abstract

In this work, we proposed a single-ended read disturb-free 9T SRAM cell for bit-interleaving application. A column-aware feedback-cutoff write scheme is employed in the cell to achieve higher write margin and non-intrusive bit-interleaving configuration. And a dynamic read-decoupled assist scheme is utilized by cutting loop to relax the interdependence between stability and read current, resulting in robust read operation and better read performance simultaneously. Moreover, the lower write and leakage energy consumptions are also achieved. We compared area, stability, SNM sensitivity and energy consumption between proposed 9T and standard 6T bit-cells. The write ability of 9T cell is 1.40× higher that of 6T cell at 1.0 V, and 8.16× higher at 0.3 V. The write and leakage energy dissipations are 26% and 13% lower than that of 6T at 1.0 V. In addition, robust read and better process variation tolerance are provided for proposed design with area penalty.

Introduction

Low-power and robust SRAM designs have drawn great research attention in the last decades. Especially the explosion of the mobile devices and portable electronic market extremely urges the increasing requirements of less power-hungry architecture. The adoption of supply voltage scaling has been proved to be the highest effectiveness in energy saving since it can reduce the dynamic power quadratically and leakage current exponentially [1]. However, with the miniaturization of devices, the variability of SRAMs in process parameters and threshold voltage together with I_on–I_off ratio increase severely, which degrades the Static Noise Margin (SNM) dramatically [2]. Furthermore, the SNMs are linearly dependent on the supply voltage, scaling down which to save power has exerted an adverse influence on the cell stability. So, how to maintain the cell stability and simultaneously keep an ultra-low power consumption become the main themes of SRAM designs in this scenario that voltage reduction along with device scaling are associated with decreasing signal charge.

In conventional 6-Transistors (6T) SRAM design, the conflicting requirements of read stability and write ability make the cell prone to unstablity and limit the minimum operating voltage (V_min) of the cell, which is becoming a catastrophic bottleneck for a 6T SRAM. With increased process variations and lower V_min constraint, it is extremely difficult to balance the read stability and write ability requirements of a cell by delicate transistor sizing. To solve the aforementioned conflict in SRAM design, many other more-than-6T SRAM cells have been proposed in [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16]. These SRAM cells isolated the read port and write port and hence the read stability and write ability could be optimized individually without affecting each other. However, most of them can only be implemented in a word-line sharing structure, but do not support bit-interleaving (or column-selection) which is always preferred to improve the SRAM׳s soft error immunity.

As far as the soft error is concerned, it becomes more critical with the reduction in supply voltage. As reported in [17], the soft error rate increases by 18% for every 10% supply voltage reduction. Especially in advanced technology, the capacitance of storage nodes becomes less, which makes the SRAM׳s poorer resistance to soft error pronounced. The bit-interleaving scheme can provide the SRAM׳s soft error protection effectively since it can spatially separate bits of a word in the row and only simple single-bit error correction coding (ECC) is required. In the above-mention SRAMs, the stored data of unselected cells would potentially be upset during the write operation when bit-interleaving configuration is used, which we called half-selected disturbance. Of course, some other SRAM cells with bit-interleaving have been presented in [18], [19], [20], [21], [22] in the past. Nonetheless, these cells introduce write performance degradation, largely area overhead, or additional peripheral circuits to support their operations.

In this paper, we present a new read disturb-free 9T SRAM cell with bit-interleaving capability. It exploits a column-aware feedback-cutoff scheme to perform write operation, resulting in write margin improvement and non-destructive bit-interleaving configuration. In addition, a dynamic read disturb-free scheme is employed in the cell, which results that the cell has a robust read operation and larger read current without read margin sacrificed. Experimental results show that our proposed design exhibits considerable improvement in write ability, read robustness, write and leakage energy consumption, as well as better process variation tolerance.

An overview of this paper is constructed as follows. Section 2 elaborates the circuit design and operation principles of the proposed cell, and an extensive discussion of cell stability and performance, including simulation results, is described in Section 3. Section 4 summarizes the paper.