Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology

Abstract

A PVT detection and compensation technique is proposed to automatically adjust the slew rate of a high-speed 2×VDD output buffer. Based on the detected PVT (Process, Voltage, Temperature) corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the slew rate of the output signal is adaptive. The proposed design is implemented using a typical 40 nm CMOS process to justify the slew rate compensation performance. By on-silicon measurements, the data rate is 500/460 MHz given 0.9/1.8 V supply voltage with a 20 pF load. Particularly, the maximum slew rate improvement is 8%, the core area of the proposed design is 0.052×0.254 mm², the maximum slew rate is 0.53 (V/ns), and the area overhead is only 31% for one single output buffer.

Introduction

Many transistors have been integrated on a single die particularly when advanced CMOS technology is employed. What even better is that the circuits consisting of advanced transistors operate faster than ever. The nano-scale CMOS technology undoubtfully provides these advantages, e.g., high operating speed, low power supply voltage, and small area in system-on-chip (SoC) integration. However, in a PCB-based system, all the chips are unlikely fabricated by the same advanced process. That is, some of the chips or discretes in a PCB-based system were fabricated by not-so-advanced processes, e.g., 5 V or 3 V CMOS process. Therefore, buffers (namely, level converter) for the chips fabricated by the advanced processes to accommodate high or low voltage swings from “older” circuits are needed in such a scenario, as shown in Fig. 1 [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11]. Notably, these buffer will occupy a significant portion of the PCB.

Besides, I/O interfaces must be designed to prevent hazards such as leakage current, and electrical overstress on the gate oxide, and offset caused by applied signals with different voltage levels [12]. These hazards will become even worse if the nanomerer CMOS technology is used and PVT variations appear [13], [14], [15], [16]. However, most of the prior designs did not consider the slew rate deviation caused by the PVT variation [17], [18], [19], [20], [21], [22]. In fact, PVT variations have been proved to affect the slew rate of the output buffer severely, as shown in Fig. 2 [17], [23]. Thus, many recent works have been proposed to enhance the capability against PVT variation and enlarge the acceptable envelope as much as possible to elevate the yield. Though delay-based methods have been widely utilized to the detect PVT variation [18], [23], those methods can only recognize three corners, i.e., TT, FF, and SS. The FS and SF corners were left unsolved in these works. To resolve this problem, we propose a novel corner detection technique to detect all process corners, i.e., TT, FF, SS, SF, and FS, in this work. Another problem of the prior work is that the transmitting and receiving speeds were not fast enough to meet certain high-speed specifications, e.g., PCI-express, which might be up to 266 MHz [24], [25]. Apparently, high speed operation becomes another demand for mixed-voltage I/O buffers besides the PVT detection and the slew rate compensation.

In this study, we propose a high-speed 2×VDD output buffer with self-adjust slew rate using 40-nm CMOS technology. By using the compensation mechanism as well as the process corner detectors, the slew rate of the output buffer is self-adjusted given a 500 MHz data rate.