Design and implementation of a micro-power CMOS voltage reference circuit based on thermal compensation of Vgs

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Abstract

In this work a simple all MOS voltage reference circuit has been proposed. To obtain reference output voltage, the thermal compensation has been generated by using a series composite NMOSTs. The voltage reference circuit has been fabricated in a standard 0.18 μm CMOS technology. The proposed circuit is capable of working for the supply voltage ranging from 1.25 V to 2 V. The maximum power dissipation of the proposed circuit is 0.48 μW at the supply voltage of 2 V. The measurement has been performed over a set of 10 samples. It resulted in the mean temperature coefficient (TC) of 19.302 ppm/°C for the temperature range of −40 °C to 85 °C. The measured mean line sensitivity is 2.217 mV/V for the supply voltage ranging from 1.25 V to 2 V at the room temperature. The measured mean power supply rejection ratio at 10 Hz and 1 MHz is −55.31 dB and −16.67 dB respectively for the supply voltage of 1.8 V. Moreover, the measured mean noise density without any filtering capacitor at 100 Hz and 100 kHz are 12.39μV/Hz and 0.39μV/Hz respectively. Due to its simple circuit implementation, the active area of the circuit is 0.0077 mm2.

Introduction

The application of voltage reference circuits can be found in a variety of circuits and systems, including voltage regulators, analog to digital (A/D), digital to analog (D/A) converters, voltage to frequency converters, power supply supervisory circuits, power converters and other circuits, which require the supply and the temperature independent on-chip voltage source [1]. The voltage reference circuits with less Si area, low power consumption and ease in implementation are always in demand.

In general, the bandgap voltage reference circuits are widely used for generating an on-chip reference voltage. They have very stable performance against the supply, the temperature and the process variations [2]. Theoretically, in it the reference voltage is equal to the bandgap voltage of the semiconductor [3]. The reference output voltage generated from the bandgap reference circuit is the weighted sum of the negative and the positive temperature coefficients (TC). In circuit level implementation, the negative TC is generated from the base-emitter voltage (VBE), the positive TC is obtained from the thermal voltage (VT) and the resistors act as a weighing function to generate the temperature independent output voltage [4]. The non-linear temperature characteristics of the base-emitter voltage and the resistors affect the performance of the bandgap reference circuit. The low temperature coefficient of the output voltage is achieved by using the temperature compensation of one or more temperature dependent parameter [5], [6], [7]. Consequently, the bandgap reference circuit offers the low temperature coefficient at the cost of large silicon area, high power consumption and a complex circuit implementation.

To solve these issues, the CMOS based realization of the voltage reference circuits has been suggested as an alternative to the bandgap voltage reference circuits in the literature. The CMOS voltage reference designs use the principle of the threshold voltage subtraction [8] or the weighted difference of the gate-source voltages [9] or the mutual compensation of the mobility and the threshold voltage [10] to generate the reference output voltage. In the threshold voltage subtraction method, the reference output voltage is proportional to the difference of the threshold voltages [11]. These circuits are designed by using the transistors with the different threshold voltages hence they require additional fabrication steps [12]. Similarly, for the circuit based on the ΔVgs method, the reference output voltage is proportional to the difference of the gate-source voltages of NMOST and PMOST. In the circuit, the thermal gradient of the gate-source voltage of the NMOST is weighted by the resistors and is made equal to the thermal gradient of the gate-source of the PMOST to obtain the temperature independent reference output voltage. The ΔVgs method is very simple in implementation, but it requires the careful design of the current bias circuit [9].

The proposed circuit comes under the category of the CMOS based realization of the voltage reference circuit. In this work, a simple voltage reference configuration has been designed which is capable of addressing the issues of the bandgap and the CMOS based voltage reference circuits. It proposes the principle that if the PTAT current flows through the diode connected series composite NMOSTs, then the temperature compensation can be achieved for the gate-source voltage (Vgs) of the composite NMOSTs by the proper selection of the aspect ratios of NMOSTs used in the stack. Hence, it will cause Vgs to be acting as the reference voltage. The simplicity of implementation enables this circuit to be used as an elementary circuit block in an ON-chip power management circuit. The rest of the work is arranged as follows: Section 2 describes the circuit configuration and the principle of proposed voltage reference, Section 3 shows the measured performance of the proposed architecture finally the conclusions are made in Section 4.

Section snippets

Circuit implementation and analysis

The schematic of the proposed voltage reference can be seen in Fig. 1. It is composed of three parts: the start-up, the resistorless beta multiplier and the temperature compensation circuit. The Beta Multiplier Circuit (BMR) has two operating points due to the presence of the positive feedback [13]. Thus, the start-up circuit is required to determine the initial state. The start-up circuit used in the proposed architecture consists of PMOSTs Ms1, Ms2 and capacitor Cs. It is based on the RC time

Measurement results

A set of 10 prototype chips was successfully implemented in a standard 0.18 μm CMOS process. The micrograph of the proposed circuit is shown in Fig. 2. The active chip area is only 0.0077 mm2, since fewer number of transistors are required for implementing the architecture. In Fig. 3, the variation of the reference voltage (Vref) with respect to the supply voltage (Vdd) at the room temperature is reported. It can be observed from Fig. 3 that the proposed circuit starts working properly from Vdd=

Conclusion

An all-MOS simple architecture for the voltage reference circuit without any parasitic vertical bipolar transistors and diodes has been proposed in this work. The voltage reference circuit is designed using the resistorless beta multiplier and the diode-connected series composite NMOSTs. The reference voltage is the gate-source voltage of the series composite NMOSTs. The proposed reference voltage circuit is capable of working at the supply voltage varying from 1.25 V to 2 V, with the measured

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