A low phase noise and low spur PLL with auto frequency control circuit for L1-band GPS receiver

Abstract

A low phase noise and low spur phase-locked loop (PLL) for L1-band global positioning system receiver is proposed in this paper. For obtaining low phase noise for PLL, All-PMOS LC-VCO with varactor-smoothing technique and noise-filtering technique is adopted. To reduce the reference spur, a low current-mismatch charge pump is carefully designed. A quasi-closed-loop auto frequency control circuit is used to accelerate the lock process of PLL. The PLL is fabricated in 180 nm CMOS Mixed-Signal process while it operates under 1.8 V supply voltage. The measured output frequency of PLL is 1.571 GHz and output power is −1.418 dBm. The in-band phase noise is −98.1 dBc/Hz @ 100 kHz, while the out-band phase noise is −130.3 dBc/Hz @ 1 MHz. The reference spur is −75.8 dBc at 16.368 MHz offset. When quasi closed-loop AFC is working, the measured lock time is about 10.2 μs.

Introduction

The L1-band signal of global positioning system (GPS) is widely used in the field of civil navigation. GPS receiver must have low noise figure to obtain accurate position information from weak satellite signal of L1-band. Regarded as an essential building block, phase-locked loop (PLL) is usually used to generate local oscillation signal in GPS radio front-end. However, the IF signals spectrum in GPS radio front-end may be corrupted by the spur tones of PLL, while the carrier-to-noise density radio (C/N₀) may also be degraded by the phase noise of PLL [1]. As the phase noise of VCO is one of main noise sources for PLL, a low phase noise VCO must be designed. All-PMOS topology and noise-filtering technique are adopted in the VCO structure. The tuning sensitivity (K_VCO) is another important parameter for the phase noise of VCO. When K_VCO is large, phase noise of VCO may deteriorate due to the AM–FM modulation [2]. To reduce K_VCO, a small size varactor is adopted. However the nonlinearity of varactor still makes K_VCO change sharply inside the voltage control range and degrades essential PLL features like phase noise [3]. So the varactor-smoothing technique is adopted to equalize K_VCO. Reference spur of PLL is concerned with non-idealities of the charge-pump (CP) [4]. Non-idealities of the phase frequency detector (PFD) and CP can be partly solved by time-delay technique and low current-mismatch technique.

A switch-capacitor array bank is adopted to cover the desired frequency tuning range in low K_VCO condition. The automatic frequency calibration circuit (AFC) can find optimum frequency control code and ensure VCO to operate in the appropriate frequency sub-band. Reported methods for AFC can be categorized into open-loop type and closed-loop type [5]. In typical open-loop method, counters are used to compare the frequency of divided VCO signal with a reference signal. Whole process of counting may take long time [6]. The closed-loop AFC method is always chosen for its simplicity. However, the lock process of closed-loop AFC may still take long time because the loop setting time depends on the loop design parameters such as loop bandwidth and initial value of control voltage [7]. Therefore, a quasi-closed-loop AFC method is proposed to accelerate calibration process.

In this paper, a low phase noise and low spur PLL with AFC is designed for L1-band GPS receiver. First, the detailed design parameters of PLL are calculated. Secondly a low phase noise VCO, a prescaler, a output buffer for test and a divider 96 are described. To shorten the lock time of PLL, the quasi-closed-loop AFC method is used. Additionally, phase-frequency detector with delay chain and low current-mismatch charge pump are designed to reduce the reference spur. Finally, PLL is implemented in a 180 nm CMOS Mixed-Signal process and measurements of chip are shown.