Ka-band frequency synthesizer involving a varactorless LC-type voltage-controlled oscillator and phase rotation

Highlights

• The work comprises a varactorless VCO, frequency doubler, and programmable divider.

• Channel switching uses a multiphase selection, high-speed programmable divider.

• The VCO uses a tunable transformer-base inductor and novel varactorless technique.

Abstract

This paper discusses the design and fabrication of a high-frequency wide-range frequency synthesizer based on a phase locked loop (PLL), varactorless LC-type voltage-controlled oscillator, and push–push frequency doubler. In addition, a high-speed programmable divider using multiphase selection is employed for channel switching. The proposed circuits were fabricated in a standard 90-nm CMOS process with a chip area of 0.8 mm×1.1 mm. The PLL dissipated 60 mW when the supply was 1.2 V. The measured phase noise of the frequency synthesizer at a frequency of 17.64 GHz and offset of 1 MHz was −97 dBc/Hz.

Introduction

Most wireless transceivers include a frequency synthesizer for generating a local oscillator (LO) signal from a low-frequency crystal oscillator. The receiver is based on a dual-conversion architecture, which reduces the system complexity substantially, and a single LO can be used to simplify frequency planning and building block design [1]. Fig. 1 depicts a receiver architecture with two down-conversion stages; two LO frequencies (f₁ and f₂=f₁/2) are used to generate quadrature phases.

In Fig. 1(a), the quadrature LO is generated by a divide-by-two circuit, avoiding the power-hungry polyphase filter [2]. LO-related problems are so severe at millimeter-wave frequencies that the choice of the receive (RX) and transmit (TX) topologies becomes closely intertwined with the LO design. The frequency synthesizer is of the phase locked loop (PLL) type, which is one of the most power-consuming blocks in the transceiver. High-frequency components for PLL design are critical in the trade-off between high frequency, low power, and wide-range operations.

To ameliorate the aforementioned difficulties, an alternative approach, depicted in Fig. 1(b), uses a simple and low-cost architecture employing a voltage-controlled oscillator (VCO) as the second LO and a frequency doubler (FD) as the first LO. This alternative relies on a frequency multiplier circuit driven by the VCO running at a lower frequency [3]. As a result, a half-rate VCO combined with a frequency doubler can provide a more reasonable tuning range than can a full-rate VCO with a divide-by-2 circuit. In the frequency-multiplying circuits, the most effective solution exploits the nonlinearity of active devices to generate harmonics of the input signal.

To maximize both the tuning range and operating frequency of a VCO, appropriately designing the capacitances in the tank is crucial. The capacitances can be formed from an effective parasitic capacitor and a varactor, and their values can be considered as the sum of a voltage-controlled variable capacitance and a nonvariable capacitance. The main contribution to the nonvariable capacitance derives from the parasitic effects of the inductor, varactor, and transistors; this capacitance limits the tuning range of the VCO, even reducing the operating frequency, because it cannot be varied by the controlled voltage. The VCO has the disadvantage of a trade-off between the dynamic range and operating frequency. However, this disadvantage can be overcome by using standard CMOS processes. Thus, a varactorless LC-type VCO featuring a tuned-transducer topology is proposed in this paper [4], [5].

Because most wireless systems operate in a narrow frequency band, the frequency doubler of the VCO, which is narrowband, can be used to achieve a trade-off between the bandwidth and the power and maximal operating frequency. Consequently, a higher frequency and lower power operation can be achieved.

A high-frequency programmable divider capable of high-resolution frequency switching is a critical component in PLL applications in wireless communication. The divide-by-two scheme involving a toggle flip-flop or injection division is generally employed in high-frequency prescalers because of its simple architecture. However, such prescalers have a fixed division ratio and cannot provide dual-mode functionality when used as swallow dividers. Consequently, the overall resolution of a high-speed frequency synthesizer is reduced.

In this study, a frequency synthesizer comprising a varactorless VCO, frequency doubler, and high-frequency programmable divider was demonstrated; the frequency synthesizer was fabricated using a 90-nm CMOS process for high-frequency operation. The circuits involved exhibited several improved features compared with existing circuits. First, the varactorless VCO was developed using a combination of mutual-negative-resistance [6] and negative-transconductance techniques to extend the operating frequency range [7]. Second, the frequency doubler behind the VCO had a push-push structure with a notch filter to achieve high fundamental rejection [8]. In addition, to maintain the inherent channel resolution for the PLL, a high-frequency multimodulus divider and a phase rotation technique were used to enable the phase selector to operate the multichannel PLL. The remainder of this paper is organized as follows. The basic concept of the frequency synthesizer system architecture is presented in Section 2. Section 3 describes implementing the building blocks. Experimental results are presented in Section 4, and Section 5 concludes the paper.