Elsevier

Microelectronics Journal

Volume 50, April 2016, Pages 60-65
Microelectronics Journal

Analytical models for channel potential, threshold voltage, and subthreshold swing of junctionless triple-gate FinFETs

https://doi.org/10.1016/j.mejo.2016.02.003Get rights and content

Abstract

Analytical models for channel potential, threshold voltage, and subthreshold swing of the short-channel fin-shaped field-effect transistor (FinFET) are obtained. The analytical model results are verified against simulations and good agreements are observed. Analytical expressions for subthreshold swing, drain induced barrier lowering effect, and threshold voltage roll-off characteristics are presented. The explicit expressions for threshold voltage and subthreshold swing make the model useful in the practical applications of the device.

Introduction

As the channel length of metal–oxide–semiconductor field-effect transistors (MOSFETs) scales down to the deca-nanometer regimes, short channel effects (SCEs), carrier mobility degradation, and currents tunneling through the extremely thin gate oxide become much more serious [1]. To solve these problems, a new type of MOSFET, the triple-gate FinFET, has been proposed, studied and adapted as a technical solution for the 22 nm technology node and beyond [2], [3], [4], [5], [6], [7], [8], [9]. However, as MOSFETs continue to scale down to the nanometer regimes, the fabrication processes of the source/drain (S/D) of the traditional inversion-mode (IM) transistor are rather complicated; the large contact resistances of S/D of the IM transistor degrade the MOSFETs; and the thermal budget of the traditional S/D will be a heavy burden. All these problems will limit the use of the triple-gate FinFETs. To tackle these problems and to improve the device performance, the junctionless (JL) MOSFET was put forward and explored to a great extent [10], [11], [12], [13], [14], [15], [16], [17]. Unlike the traditional IM transistor where accepters and donors are doped in the channel and the S/D regions, respectively, a JL transistor is doped with the same type of dopant throughout the channel and S/D regions. Therefore, the fabrication processes are simplified and the S/D contact resistances are decreased.

To facilitate the applications of the device in integrated circuits, analytical models for channel potential, threshold voltage, Vth, and subthreshold swing, SS, are inevitably needed in the practical use of the device. Lots of theoretical researches have been carried out on the characteristics of drain current, IDS, Vth, and SS of the JL double-gate (DG) MOSFETs in the literature [18], [19], [20], [21]. Explorations on the analytical models of the JL surrounding-gate (SG) or nanowire MOSFETs have been conducted in [22], [23], [24], [25], [26]. In our previous work, we obtained the analytical models of Vth and SS for JL SG transistors [27]. Trevisoli and others investigated the IDS model for triple-gate JL nanowire transistors [28]. They obtained the IDS model based on the approach of adding the solution of the 3-D Laplace equation to the solution of the 2-D Poisson equation, instead of solving the 3-D Poisson equation directly. The analytical expressions for Vth and SS of the JL FinFET with a short channel are desired in the applications of the device.

In this work, we focus our research on the Vth and SS of the JL FinFET with a short channel. We solve the 3-D Poisson equation directly and obtain an analytical expression for channel potential. Then, we achieve the analytical expression for Vth based on the new definition we put forward in our previous work [27]. After that, analytical expressions for SS, drain induced barrier lowering effect (DIBL) and Vth roll-off characteristics are obtained.

Section snippets

Analytical model

The sketches of the JL FinFET similar to those in [8] are shown in Fig. 1(a) and (b). The Cartesian axes of x, y, and z are along the channel length, width, and height directions, respectively. The channel material of the device is heavily n-doped silicon. The channel is surrounded with a very thin oxide layer and the oxide is then enclosed with a fin-shaped gate, which can either be a metal or a heavily doped polysilicon.

The Poisson equation in the channel is2ϕx2+2ϕy2+2ϕz2=qNDεsi[1exp(ϕ

Verification and results

Our models are verified against a simulation tool, Sentaurus [32]. In the simulation, hydrodynamic model is used. Trap assisted Auger processes and tunneling, as well as band to band tunneling is included. The dependencies of carriers׳ mobility on the doping concentration, temperature, normal and high electric field, are considered.

In the simulation, a heavily doped p+ polysilicon is chosen for the gate. Unless stated otherwise, the parameter values used are shown in Table 1.

Fig. 2 shows the

Discussion and concluding remarks

An analytical expression for channel potential is obtained by solving a 3-D Poisson equation without gradual channel approximation. Based on the potential model, analytical expressions for Vth, DIBL effect, Vth roll-off characteristics, and SS are presented. The proposed models have been verified against the commercial device simulator and good agreements are observed. The explicit expressions for Vth and SS make the models useful in the applications of the device.

Model and simulation results

Acknowledgment

Precious support from Shanghai Science Foundation under Grant No. 14ZR1402600 is appreciated. This work is supported in part by National Natural Science Foundation of China (Grant No. 61571137).

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