Elsevier

Microelectronics Journal

Volume 52, June 2016, Pages 91-103
Microelectronics Journal

A cellular automata based highly accurate memory test hardware realizing March C

https://doi.org/10.1016/j.mejo.2016.03.009Get rights and content

Abstract

This work reports a highly accurate test structure for high speed memories. The theoretical bases of the design are the March algorithm and cellular automata (CA) proposed by von Neumann in 1950s. Theory of 3 and 5-neighborhood CA, employed for the current application, has been developed to enhance the self-testability of memory test logic. The special class of single length cycle attractor cellular automata, introduced in this work, accepts status of each memory word and evaluates it to decide on the faults in the memory. The extension of CA neighborhood to 5 enables propagation of the effect of faults in memory or in the test logic to the error line of the test structure. This overcomes the inability of classical memory test hardware designed with the exor and or logic.

Introduction

The exponential growth of compaction density in memories compels the designers to devise expensive test logic. The traditional memory testing algorithms [1], [2] are the Zero-One (Scan Test or MSCAN [3]), Checkerboard, Walking 1/0 [4], GALPAT, Sliding Diagonal [5], and many others. Zero-one and Checkerboard tests require linear time but achieve poor fault coverage. GALPAT and Walking 1/0 tests are of O(n2) and O(n32) complexity, where n is the size of memory. However, the March test [6] is found to be the most powerful as well as efficient than the classical pattern based test techniques. It is extensively used for functional testing of semiconductor memories and provides a linear time solution with high fault coverage.

Comparatively recent approach, introduced to improve the testability, is the redesign and augmentation of peripheral circuits in and around the RAM. This is popularly referred to as the design for testability (DFT). The memory BIST (built-in self-test) approaches [7], [8], [9] add even more extra hardware with the target to reduce the test time of a memory device. ABIST (Array BIST) [10], used for embedded memories, is an effective form of MBIST (memory BIST). However, the advantages of ABIST are often offset by its overhead requirements.

March test is also an MBIST algorithm. A large variations of March test algorithms are reported in the literature [6], [11]. The main goal of these approaches is to reduce the memory testing time. The authors in [12] introduced March C with time complexity of the order of 11n (n, number of memory bits) to target SAFs (stuck-at faults), TFs (transition faults), and all CFs (coupling faults). This is further improved in March C by [5] to achieve the complexity of 10n. The other notable work on March algorithms are the [13], [14], [15].

In 1980s, Wolfram [16] studied a family of simple 1-dimensional cellular automata (CA) that could simulate complex system behaviors. A special class of Wolfram׳s 3-neighborhood CA, called the linear/additive CA had been employed for developing effective methodologies for VLSI design [17]. The CA had also been found effective for efficient design of fault detection and diagnosis schemes in VLSI circuits [18], [19], [20]. This motivates us to address the issue of high speed fault detection in memories and to devise an efficient test logic around CA that can reduce test time simultaneously satisfying the requirement of insignificant test overhead.

The test design, proposed in this work, is developed around a special class of 1-dimensional cellular automata referred to as the single length cycle attractor CA. The CA is configured for realizing the March test [11]. It runs on the data (memory word) read from a memory location and computes the status of the memory cells (faulty or non-faulty). The properties of single length cycle attractor CA are then exploited to memorize the status of the word. The final state, at the end of test run, indicates faults (if any) in memory.

The CA based proposed test structure computes the status of memory words in parallel with the memory read/write operation of a March element that effectively reduces the number of comparisons required in the conventional test designs. The CA neighborhood is extended to 5 to enable identification of faults (if any) in a memory word even if the test logic is defective. The regular and modular structure of CA, enabling segmentation of the test hardware, realizes the memory testing in reduced test time as well as a scalable test design for high speed memories. It better suits for low cost VLSI implementation of the test hardware for a memory device that is inherently regular in structure. The CA based test design is introduced in Section 4 following a brief on March test in Section 3. The details of the design developed around the single length cycle cellular automata are reported in Section 5. Section 6 reports performance in terms of test accuracy of the proposed structure. The test design around 5-neighborhood CA with enhanced test accuracy is detailed out in Section 7. The next section introduces the preliminaries of CA that have relevance for the current work.

Section snippets

CA preliminaries

A cellular automaton (CA) evolves in discrete space and time, and can be viewed as an autonomous finite state machine (FSM). Each CA cell stores a discrete variable at time t that refers to the present state (PS). The next state (NS) of the cell at (t+1) is affected by its state and the states of its neighbors at t. In this work, we consider the 1-dimensional CA, where a cell is having two states – 0 or 1. The next state of ith CA cell in 3-neighborhood is Sit+1=fi(Si1t,Sit,Si+1t)Si1t, Sit

March test

The March test [5] is found to be the most powerful scheme for fault detection in memories. It is extensively used for functional testing and provides a linear time solution with high fault coverage. In the current design, we consider effective realization of March C for determining correctness of memory function. However, any March algorithm, that is considered to be efficient in terms of fault coverage or any other parameter, can be realizable in the framework of proposed cellular automata

Overview of test design

The proposed design of test structure for memory is developed around the cellular automata (CA), introduced in Section 2. The test scheme targets realization of the March test that can be applicable to any variation of March algorithm. For the example design, the March C is referred in this work. The architecture of the design is shown in Fig. 4. In each read operation ‘r0’ or ‘r1’ of March C, the test hardware stores the n-bit word of memory to a register RG (Fig. 4). Each bit in RG is used

The CA selection for test design

Section 4 identifies the requirements for the test design. The properties of CA that can satisfy the requirements are explored with introduction of the concept of Explicit Rule Vector Graph (ERVG).

Accuracy in testing

The test hardware (Fig. 10) designed around the 3-neighborhood cellular automata (CA), realizing March C, if subjected to different faults, may show inaccurate test result. The evaluation of the CA based test structure, while subjected to single s-a-f at error line, irrespective of the single s-a-f at memory under test, is reported in Table 3. The first two columns of Table 3 define the status of memory and the test hardware respectively. The test result (decision of the CA based test

Test design with 5-neighborhood CA

This section reports a test logic that ensures better accuracy in memory testing as well as fault tolerance of the test structure. The neighborhood of cellular automata (CA), employed for the test design in 4 Overview of test design, 5 The CA selection for test design, 6 Accuracy in testing, is extended to 5 to enhance the accuracy in testing as well as fault tolerance.

In 5-neighborhood, the next state Sit+1 of ith CA cell at time t+1 depends on its present states and its 4 nearest neighbors ((i

Conclusion

This work proposes an efficient hardware for March algorithm. The solution is developed around the regular structure of cellular automata (CA). Theory has been developed to explore the special class of CA rules, forming 2-attractor CA and the single single length cycle attractor CA, that suit for the design. The proposed test structure enables the high speed testing of memories at very low cost and outperforms the conventional test design approach.

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