Elsevier

Microelectronics Journal

Volume 59, January 2017, Pages 40-46
Microelectronics Journal

A 0.5-V 9.3-ENOB 68-nW 10-kS/s SAR ADC in 0.18-μm CMOS for biomedical applications

https://doi.org/10.1016/j.mejo.2016.11.007Get rights and content

Abstract

This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) intended for use in wearable biomedical circuits. In order to achieve the nanowatt range power consumption, an energy-efficiency modified VCM-based switching scheme is proposed. In addition, a fully dynamic comparator and a dynamic register are used to eliminate the static power consumption. To improve the signal linearity in such a low supply voltage, a double-boost bootstrapped switch is proposed. A prototype of the proposed SAR ADC was fabricated in 0.18 µm 1P6M CMOS technology within a bio-sensor front-end circuit, which occupies an active area of 370×390 µm2. The SAR ADC achieves 57.8 dB SNDR and consumes 68nW at 0.5 V supply voltage and 10 kHz sampling rate, resulting in a figure-of-merits (FOM) of 10.8fJ/conversion-step.

Introduction

In recently years, there is a growing interest in the development of integrated circuits for wearable and implantable biosensors, which provides remote health monitoring of a patient's state for a long period without any restriction on one's normal activities. Moreover, the wearable or implantable devices allow bio-signal monitoring to be done daily than limiting it within the clinical environment, which opens up the market for portable medical electronics to the ordinary people. Since these circuits are likely to be powered by portable batteries or energy harvest circuits, ultra-low power consumption is required to make it work normally for several years [1]. In a biosensor system, analog-to-digital converter (ADC) is the key building block which acts as a bridge between analog front-end and digital back-end [2]. Fig. 1 shows the block diagram of the biosensor system with a SAR ADC.

Conversion of the low-frequency bio-potential signals does not need high speed, but requires ultra-low-power operation for biomedical applications. Compared to other ADC architectures [2], successive approximation register (SAR) analog-to-digital converter (ADC) is an outstanding candidate for wearable or implantable biosensor due to its simple structure, energy efficiency and compatibility with technology scaling [3], [4]. Work [3] proposed an ultra-low-power SAR-ADC with sampling rate of 40kS/s for wireless bio-potential network, which is based on a fully dynamic logic and consumes merely 97nW in 12-bit resolution. In addition, various schemes have been proposed to improve the SAR ADC power efficiency [5], [6], [7], [8]. However, there are still several challenges to efficiently reduce the speed and bandwidth for ultra-low-power operation using inherently fast devices in advanced CMOS technologies.

Subthreshold operation has recently become an acknowledged solution for low-power applications because it significantly reduces the current consumption of the transistor [9]. In addition, the front-end system, with its scaled supply voltage, will be suitable for use in a wireless bio-potential SoC [1]. In order to achieve nanowatt range power consumption, the supply voltage is scaled to 0.5 V. Operating in the subthreshold region limits the circuit bandwidth. Fortunately, since the informal frequency spectrum of bio-signals lie at very-low frequency range, subthreshold operation does not affect the performance of the SAR ADC.

Since the frequency spectrum of bio-signals lie at low levels from sub Hertz to couple of hundred Hrtz, the sampling rate should be set to a higher value to achieve a better performance. However, large sampling rate results in large power consumption, thus the sampling rate should be set to a relatively small value to reduce the power consumption. Therefore, the sampling rate of this SAR ADC is set to 10k Hz based on the trade-off between SAR ADC performance and power consumption.

A dynamic comparator and a fully dynamic SAR logic are used to prevent the static power consumption. Moreover, a high power-efficiency modified VCM-based switching scheme is proposed. Since the supply voltage is close to the MOSFET subthreshold voltage, a double-boost bootstrapped sampling switch is proposed to improve the ADC performance. The paper is organized as follows: Section 2 shows the overall SAR ADC architecture. Section 3 describes the capacitor switching procedure and analyzes its power and linearity. The key building blocks are discussed in Section 4. The measurement results are given in Section 5. Finally, a conclusion is made in Section 6.

Section snippets

Overall SAR ADC architecture

Fig. 2 shows the block diagram of the proposed SAR ADC. It is implemented in a fully differential architecture to enhance the common-mode noise immunity and improve the linearity. The SAR ADC comprises a bootstrapped sampling switch, a binary weighted capacitive DAC, a dynamic latch comparator and a low-leakage synchronous SAR logic. The input signal is sampled on the top-plate nodes of the capacitor array by bootstrapped switches, and the comparator compares the voltage on the differential

Modified VCM-based switching scheme

In recent years, biomedical applications are drawing the research attention, and many outstanding switching schemes are proposed to improve the power efficiency of SAR ADC. However, most of these works consider only the current switching energy while ignoring the reset energy for next conversion step, which are not practical in reality. Several excellent works take both of switching energy and reset energy into consideration and still achieve a good reduction of the energy [5], [6]. Work [12]

Bootstrapped switch

Since the supply voltage is scaled to 500 mV, sampling switch transistor becomes the major bottleneck in the SAR ADC, because the non-ideal switching effects and the charge injection deteriorate the input signal. The bootstrapped switch is used to reduce the on-resistance variation, which helps maintain a constant resistance to improve the dynamic linearity. Supposing the switch transistor works in triode region and its drain-source resistance Ron can be expressed asRon=1μnCoxWL(VGSVTH)

In order

Measurement results

The 10-bit SAR ADC has been implemented in a bio-signal acquisition front-end circuit using SMIC 0.18 µm CMOS technology, the SAR ADC occupies an active die area of 370×390 µm2. Fig. 11 shows the chip photo of the SAR ADC. Two bootstrapped sampling switches are placed at the left side of the circuit and the comparator is put after them. The SAR control logic and capacitor switches are placed in the middle of the chip, while the capacitor arrays are laid besides.

All capacitors implemented in DAC

Conclusion

This paper presented a 10-bit SAR ADC implemented in SMIC 0.18 µm CMOS process. The proposed SAR ADC occupies roughly 0.144 mm2 active area and consumes 68nW at 10k Hz sampling rate with a 0.5-V supply. A modified VCM-based switching scheme is proposed, which reduces the area and power consumption. A double-boost bootstrapped switch is employed to improve the linearity. The SAR ADC offers an ENOB of 9.3 bit with the Nyquist input frequency and achieve a FOM of 10.8fJ/convertion-step. Moreover,

Acknowledgments

This work was supported by the National Natural Science Foundation of China (61322405, 61234002, 61574103, 61574105).

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