Design of Testable Adder in Quantum‐dot Cellular Automata with Fault Secure Logic
Introduction
CMOS technology is reaching its limit beyond which further downscaling in feature size is impossible due to high leakage current, high power density levels and high lithography cost. Quantum-dot Cellular Automata (QCA), is considered as a viable alternative to meet the energy efficient design beyond the limit of existing CMOS technology [1], [2]. The major advantages such as low power consumption, high speed and high compaction density of QCA based design have attracted researchers to investigate its visibility and reliability constraints [3]. Recently the room temperature operable semiconductor QCA is invented which solves one of the hurdles of QCA fabrication [4]. In this paper, the semiconductor technology [5] is adopted as an implementation technology for our QCA designs with an intermediate dot size of about 5 nm which is different from magnetic QCA or molecular QCA in which dot sizes are approximately 100 nm and 2–5 nm respectively [6].
While every VLSI design has its own unique set of goals, there is a primal need for dependability in the completed product. It becomes an utmost necessity for the QCA system to address the three main impediments for exploiting its full potential as discussed in [7]. One of the blockages is the tolerance to fabrication defect along with required precision in the assembly [7]. Again, the most significant hurdle that needs to be addressed in the area of circuit testing is to provide inherent support for error detection [8]. The mentioned obstacles of fault tolerance motivate further research towards this direction.
On the other hand, wire-crossing is a major overhead [9], [10] towards the realization of a reliable system in QCA paradigm. In [11], defect characterization of different QCA components are reported where wire crossing is identified as one of the most vulnerable parts of a QCA system. The reliability of the QCA system is achieved so far by just making the individual components of the circuit, like majority voter, inverter, etc., to fault tolerant [7], [12]. In this regard, reliability of the internal communication route/channel, fanout, wire crossing etc. is neglected. As well, no such suitable methods are there to make these components more testable.
It is well known that full adders are the primary member of computational systems because of its capability to implement other operations efficiently [13], [14]. In the presence of sum (parity of three inputs) and carry output, it has never been possible to establish a parity preserve full adder considering its two main outputs (sum, carry) together. Few efforts have already been attempted in the direction of fault tolerant full adder [15], [16] without riveting its testability. The path fault secure (PFS) scheme is widely used in the conventional system network to enhance its reliability [17]. But the testability feature provided by the few existing parity preserving designs often takes the center stage ignoring the logical depth of a gate which ensures the cost-effective realization of large circuits with a fewer number of gates as well as wire-crossings. No comprehensive inherent testable scheme for QCA logic has been built up, so far.
All these above factors motivate us to design a new logic structure that can make a trade-off between the QCA design cost of testing and generation of correct primary outputs. In order to reduce the overall cost and wiring, a new testable adder logic (t-Adder) is proposed in which the primary function (sum and carry) is completely utilized with the test procedure. The goal of this work is to describe the testability of such circuits and make it more fault resistant. The major contribution of this work, around parity preserving QCA architecture, can be summarized as follows:
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A testable parity preserving full adder (t-Adder) is designed considering its primary outputs.
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Results show the effectiveness of the design in terms of cost, power and testing overhead.
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Reliability issue is addressed with the success of 100% fault coverage with only 3 (three) test vectors.
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The power dissipation of the t-Adder is analyzed which ensures low power consumption.
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To make robust fault secure t-Adder, path fault secure (PFS) scheme (first time in QCA circuit) is riveted to it.
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Further, t-Adder is used to design a simple testable ALU with high logical depth.
Section snippets
Preliminaries
Quantum dot is a region where an electron is quantum mechanically confined (Fig. 1(a)). A quantum cell consists of such quantum dots at each corner of a square and contains two free electrons [2]. The electrons can quantum-mechanically tunnel among the dots and settle either in polarization (logic 0) or in (logic 1) as shown in Fig. 1(b).
The basic structure realized with QCA is the 3-input majority gate, (Fig. 1(c)). Majority gate can be programmed such that it
Related work
Most of the research work which aims to design testable logic around QCA make use of conservative logic and parity preserving logic such as Fredkin, CQCA, MX-QCA, RM, t-QCA, PPRG, RQCA and TPC-QCA gate [21], [22], [23], [24], [25], [26], [27], [28] (Fig. 4). The Fredkin gate is a universal gate, but it is difficult to construct large circuits with the Fredkin gate [28]. Further, the fault coverage of its QCA layout is very poor under single omission cell and extra cell deposition defect [22].
Design of self-testable (t-Adder) QCA logic
Since parity preserving, reversible and conservative logic is investigated as the most widely used techniques for making the testable circuit in QCA, the following constraints are observed to make a testable adder in QCA considering sum and carry together. Lemma 4.1 A reversible full adder circuit cannot be realized with one garbage output only, i.e a reversible adder is not possible. Proof 4.2 The most important property of the reversible logic is that the number of input/s and output/s are the same [35]. Since
Testing and fault coverage
One of the most challenging hurdles that needs to be addressed in the field of circuit testing is that the conventional logic gates do not provide any inherent support for error detection. As a result, the design needs to be significantly altered to achieve error detection. Defects in QCA arise during the deposition and synthesis phase, and a majority of them occur in the deposition phase. The various types of defects which need to be dealt with include additional cell defect, cell omission
Design of ALU based on t-Adder
An arithmetic logic unit (ALU) is a fundamental building block of any computer system. ALU is responsible for performing arithmetic and logic operations such as addition, subtraction, increment, decrement, logical AND, logical OR, logical XOR, logical XNOR, etc. The proposed arithmetic logic unit is designed using four t-Adder gate as shown in Fig. 15(a). It has 10 primary inputs, 2 major outputs, and 8 garbage outputs, thus parity preserving nature of the circuit is maintained (Fig. 15(b)).
Simulation environment
QCADesigner [48], [49] is used to verify the functional behaviour of proposed QCA circuits. QCADesigner uses Hartree approximation to simulate QCA circuits in order to solve the Schrodinger equation to obtain self consistency [50], [51], [52]. QCADesigner (version 2.0.3) [48], [49] has been used to verify the correctness of the proposed QCA designs. In QCADesigner, the simulation parameters have been set as follows:
Cell Size=18×18 nm, Dot Size=5 nm, Cell Separation=2 nm, Simulation Engine=Bistable
Conclusion
This paper proposed a novel parity preserving QCA testable adder (t-Adder) with inherent fault secure capability. Only three test vectors are sufficient to detect all the single as well as multiple stuck-at faults. The primary advantage of proposed t-Adder is that the device itself can be tested 98% for single missing cell defects which is first of its kind in QCA technology. The cost effectiveness of t-Adder is evaluated comparing all the popular testable gates. The logic performance of the
Acknowledgments
This research is supported by the Department of Electronics and Information Technology, Ministry of Communications and IT, Government of India under the Visvesvaraya PhD Scheme administered by Media Lab Asia.
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