Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS☆
Introduction
In nanoscale CMOS technology, VLSI performance is significantly improved by means of further shrinking transistor feature size. However, as technology scaling down, reliability issues of circuits have become one of the major concerns for circuit designers and researchers [1], [2]. Since supply voltage and node capacitance scale down as well, the logic state of a node can be easily disturbed when a particle striking induced charges are collected by the source/drain diffusions of transistors [1]. As a result, the radiation induced single event effects, such as single event double-upset (SEDU) due to multiple-node charge sharing in a memory element (latch, flip-flop, etc.), and single event transient (SET) which is not masked by logical or electrical masking through logic gate cells, arriving at the memory element from combinational blocks, are becoming increasingly serious with technology evolution [3], [4].
Recently, based on radiation hardening by design technique, a number of schemes devoted by researchers that presented a very important contribution to single event upset (SEU) mitigation have been proposed in the literature [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], in which, some ones are SET filterable as well [10], [11], [18]. These schemes make use of interlocked hold nodes or spatial redundancy to correctly retain data, and take advantage of temporal redundancy or an existing CMOS structure to filter an SET. However, due to the close proximity in nanoscale CMOS technology, multiple node charge sharing induced SEDU is becoming more prominent especially in harsh radioactive environments, and soft error rate resulting from SEDU is rising as well [20]. Hence, existing SEU tolerant latch designs are no longer robust facing to SEDU, and can not be used as reliable ones in reliability highly required systems.
In order to further effectively tolerate SEDU, researchers have presented many novel schemes using technologies like node spacing increase, well isolation, guard rings, and multiple-modular redundancy in the literature [21], [22], [23], [24], [25], [26]. As for all the above radiation hardened latches, we can classify them into four types: 1) Latches being not SEDU hardened at all [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19]. These latches could be more easily affected by an SEDU, resulting in invalid data retaining; 2) Latches being SEDU hardened, but not fully SEDU-immune [21], [22], [23], [24], i.e. there is at least one pair of nodes can be flipped by an SEDU, resulting in invalid data retaining; 3) Latches being fully SEDU immune (i.e. no matter which pair of nodes is flipped by an SEDU, the latch retains correct data, though some flipped internal nodes cannot self-recover.) but cannot filter an SET [25], [26]; 4) Latches not only being fully SEDU immune, but also can filter an SET. As far as we know, there is no any scheme of this kind at all, and we would present a hardened latch design of this kind in this paper.
In the first three kinds of latches, Muller C-element (hereinafter referred to as MCE) [27], dual interlocked storage cell, i.e. DICE [28], and Schmitt trigger inverter (hereinafter referred to as STI) are widely used for radiation hardening. Since the first two kinds of latches are not fully SEDU-immune, the cost penalties about silicon area, power dissipation, and propagation delay are relatively smaller. The third kind of latches is fully SEDU-immune, and hence the overheads are larger. Note that, some latches of these kinds are SEU-resilient, such as high-performance, low-cost, robust and clock-gating, i.e. HLR-CG1 and HLR-CG2 in [8], highly reliable and high performance SEU hardening, i.e. HRPU in [22], and triple path DICE i.e. TPDICE in [23]. A latch is SEU resilient, which means all nodes restore back the correct data no matter which node is flipped by an SEU.
This paper presents an SEDU fully immune and SET filterable latch design in 65 nm CMOS technology. By means of a triple-input Muller C-element (TMCE), which is driven through a clock gating (CG) based TPDICE, all internal nodes and output node of the latch are not only SEU resilient, but also SEDU fully immune. Besides, taking advantage of an embedded STI on the propagation path, the latch also effectively filters an SET in transparent mode. Further, making use of a keeper connected to the output node, the latch becomes insensitive to a high impedance state (HIS). Simulation results have demonstrated SEDU fully immunity, SET filterability, and 60.41% area-power-delay product (APDP) saving, compared with the SEDU fully immune DNCS-SEI latch.
The remainder of the paper is organized as below. In Section 2, previous radiation hardened latches will be reviewed. Next, in Section 3, we introduce the principle, implementation, and reliability verification of the proposed latch. In Section 4, robustness and cost comparison results are presented, followed by conclusions in Section 5.
Section snippets
Previous hardened latches
According to the three types of latches mentioned in the previous section, this section reviews the low cost and highly reliable (LCHR) latch in [11], circuit and layout combination technique (CLCT) based hardened latch in [21], and the double-node charge sharing aware soft error interception (DNCS-SEI) latch in [26], respectively.
Proposed hardened latch design
In this section, we present the circuit structure and behavior, verifications for SEU resilience, SEDU fully immunity, SET tolerability, and HIS insensitivity of the proposed latch.
Latch evaluation and comparison
Aiming for making a fair comparison, the simulation conditions for the alternative radiation hardened latches are the same as that listed in Section 3.2, and the minimal area design rule is also applied for all the latches, which means that the minimum possible transistor sizes making the latches work properly are utilized. The reliability and cost comparison are presented in Table 1.
In Table 1, the second column data are the latch names, the third, the fourth, and the fifth column data are the
Conclusions
This paper has proposed a cost effective, SEU resilient, SEDU fully immune, HIS insensitive, and SET filterable latch in 65 nm CMOS technology. The latch mainly consists of a clock gating based TPDICE for keeping data, a triple-input Muller C-element for blocking an SEDU propagated from the TPDICE, an embedded Schmitt trigger inverter for filtering an SET, and a keeper connected to the output node to prevent the latch from being sensitive to an HIS. Simulation results have shown the SEU
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