Power-Gating Sub-Threshold Source-Coupled Logic (PG-STSCL) circuits for ultra-low-power applications

Abstract

The sub-threshold circuit design is regarded as a promising technique to provide considerable power reduction for ultra-low-power applications under tight energy constraints. This paper presents Power-Gating Sub-Threshold Source-Coupled Logic (PG-STSCL), which employs the fine-grain power gating at the gate level. It introduces isolation and retention circuits to ensure reliable propagation of data along a pipeline of power gated circuits, called a micro-pipeline. While the conventional STSCL circuits can considerably cut down the active power consumption, they have the drawback of continuous static current flow. To overcome this drawback, the proposed architecture shuts off the static current by utilizing the fine-grain power-gating technique. We have designed a 32-bit adder based on the proposed PG-STSCL gates in a 65 nm CMOS technology. The adder was simulated and compared to reference adders using standard CMOS gates, and conventional STSCL gates. Simulations demonstrated that the proposed gates provide a power reduction of 89.56% and 99.78% when compared to the standard CMOS and STSCL gates, respectively.

Introduction

Recent low-power applications such as wearable, implantable biomedical systems, IoT devices, and sensor networks are facing increasingly tighter energy constraints [[1], [2], [3], [4]]. These energy-constrained applications are either battery-operated or use an energy-harvesting source. As a result, they demand ultra-low-power (ULP) circuits. For such applications, maintaining device lifetime is often considered a higher priority than the operation speed due to the difficulty of a battery recharge or replacement. To achieve these requirements, researchers proposed circuits operating in the sub-threshold (weak inversion) regime. Sub-threshold operation using leakage current has been regarded as one of the most power-efficient approaches [[5], [6], [7]]. The minimum energy per operation point (MEP) has been achieved in the sub-threshold operation region by the studies of [1,[8], [9], [10]].

When operated under deeper sub-threshold conditions, circuits exhibit their power consumption quadratically decreasing [11]. Although the delay of the circuits tends to increase in the sub-threshold region, it is usually of less concern in the energy-constrained applications such as IoT.

The process, voltage, and temperature (PVT) variations are of the major design challenges in the sub-threshold region due to their exponential dependency on the sub-threshold current. Furthermore, the design rules for sub-threshold operation differ greatly from the design rules for nominal-voltage operation [12].

To combat the above drawbacks of sub-threshold operations, various alternative circuit structures other than conventional static CMOS circuits have been studied. The source-coupled logic (SCL), also known as MOS current-mode logic (MCML), circuit is considered as a good alternative. The SCL allows for fast and low noise operation compared to static CMOS circuits, while consuming lower power at high speed, due to its differential structure [[13], [14], [15]]. An SCL gate structure is shown in Fig. 1. In this paper, a sub-threshold SCL circuit with a micro-pipelined power gating architecture at the gate-level is proposed. It takes the low power advantage of sub-threshold operations and the high-speed advantage of SCL as explained in details in Section 4.

Static CMOS logic power consumption is mainly determined by dynamic (switching) power consumption which tends to increase quadratically with the supply voltage [1]. By reducing the power supply voltage and operating in sub-threshold regime, it can typically operate with very low power consumption. However, reducing the supply voltage increases the gate delays. The increased delays in turn require longer active period of the circuits, which leads to higher energy consumption. Therefore, there is a strong relationship among circuit parameters, such as supply voltage, operating frequency, dynamic power consumption, and gate delay. These performance parameters along with process parameters make the design optimization highly limited and inflexible. Due to the exponential relationship between the power dissipation and supply voltage in sub-threshold regime, as well as the dependency between the supply voltage and the gate delay, it is very hard to reduce the power consumption considerably. In ultra-deep sub-micron (UDSM) technologies, the sub-threshold leakage becomes excessive in conventional static CMOS logic. To overcome the sub-threshold leakage issues in UDSM conventional CMOS logic, sub-threshold source-coupled logic (STSCL) can provide a favorable alternative solution.

Recently, Tajalli et al. introduced an STSCL topology with a bulk-drain connected pMOS load that exhibits high resistivity suitable for implementing ULP digital systems [16,17].

Also, Cannillo et al. showed the applicability of sub-threshold MOS current-mode logic (ST-MCML) in sub-100 nm technologies and demonstrated the benefit of using the ST-MCML in the ULP applications [18,19].

Unfortunately, STSCL or so-called ST-MCML, however, exhibits constant static power dissipation. Therefore, STSCL suffers from poor power-efficiency when the circuit has very low switching activity or operating at low frequencies. This constant static power dissipation, if left unmanaged, would result in an excessive energy consumption in dense gate designs that operate at moderate or low frequencies.

As technology nodes move towards sub-100 nm, leakage power dissipation dominates the dynamic power dissipation. Power gating techniques have been used to shut off the static or leakage current of a circuit block, when its operation is finished and the circuit block is not switching [20]. This technique, however, is not effective for STSCL circuits. Especially for large data-path circuits such as wide adders or multipliers, the operation cycle is relatively long, and thus power gating would still incur large static current throughout the STSCL circuit block. To effectively shut-off such static current in STSCL, we propose a novel power gating technique employing a fine-grain micro-pipelined power gating which shuts off each gate stage.

This paper presents a power-gating technique for STSCL gates. Section 2 describes the properties of conventional SCL and STSCL with its performance analysis. The Power Gating for STSCL is discussed in Section 3. In Section 4, the proposed architecture for the PG-STSCL is introduced. Extensive simulations for different gates are given in Section 5 to evaluate the performance of the proposed architecture. The conclusions are provided in Section 6.