Elsevier

Microelectronics Journal

Volume 75, May 2018, Pages 87-96
Microelectronics Journal

Systematic design and optimization of operational transconductance amplifier using gm/ID design methodology

https://doi.org/10.1016/j.mejo.2018.02.002Get rights and content

Abstract

The simple square-law MOSFET model fails to describe the behavior of short channel and moderate/weak inversion devices. The gm/ID methodology is a promising technique that addresses the square-law shortcomings and bridges the gap between hand analysis and simulation. This paper describes a systematic procedure for the design of a single-stage operational-transconductance amplifier (OTA) using the gm/ID methodology. Both small signal and large signal specifications are used to constrain the design process, which is graphically illustrated using trade-off charts. The presented design procedure is automated using MATLAB, and an iterative procedure is used to take the OTA self-loading into consideration. Moreover, an automated optimization procedure is presented to maximize the speed of a unity-gain buffer under current consumption, DC gain, and input capacitance constraints. The designed circuits are verified using Cadence Spectre and the 180 nm Predictive Technology Model (PTM), where the simulation results are in close agreement with hand analysis and automation results.

Introduction

Analog IC design will always be there because we live in an analog world. Analog-to-digital converters (ADCs) and digital-to-analog converter (DACs) will always be needed (together with their associated circuits such as amplifiers, filters, references, and regulators) to interface between our analog world and our digital electronic devices. It may be thought that CMOS analog design is an art that depends on lots of experience and intuition. One reason that may support this claim is that the simple square-law MOSFET model common to most textbooks and university courses fails to describe the behavior of short channel devices, as well as devices operated in moderate and weak inversion (which are becoming increasingly popular in energy-efficient designs [[1], [2], [3]]) regardless of their channel length. On the other hand, more accurate device models are too complicated, and are not amenable to hand analysis. In addition, there is no definite systematic recipe that the designer can follow to design an analog block, even if it is a fundamental block like an operational transconductance amplifier (OTA). As a result, the analog designer has to rely on lengthy multi-variable sweeps on simulation tools, experience, and intuition to make his design work. In addition to requiring significant design time and expensive simulation tools licenses, this design methodology hinders the understanding of design trade-offs, the development of valuable designer intuition, and the systematic porting of designs from one technology node to another.

A promising methodology that addresses the previous limitations, and bridges the gap between hand analysis and simulation is the gm/ID design methodology [[4], [5], [6], [7], [8], [9]]. The basic idea of this methodology is to describe the transistor behavior using a dataset generated from simulation sweeps (or measurements) rather than inaccurate simple models. This dataset characterizes different normalized transistor parameters and figures-of-merit vs the transconductance-to-current ratio (gm/ID). The gm/ID is used as a primary design variable instead of the overdrive voltage which is common in square-law based design flow. The gm/ID can be thought as a normalized measure of the channel inversion level for all operating regions, and it directly captures the relation between the basic function of the transistor (the transconductance) and the most valuable resource (the power consumption). The gm/ID dataset is one-time generated for a given technology, and can be reused in the form of trade-off charts or lookup tables. The design process becomes a systematic procedure, where hand analysis expectations are in close agreement with simulation results.

One of the early works that discussed the gm/ID methodology was proposed by Silveira et al. in Ref. [4]. This pioneering work proposed using the gm/ID methodology for OTA design; however, several design variables were assumed without being constrained by clear circuit specifications. In addition, the details of the optimization procedure used to select the gm/ID values and the transistor sizing were not explained. Moreover, important circuit specifications such as input range, noise, and common-mode rejection were not considered. Finally, it did not consider the variation of the gm/ID characteristics with channel length, since this variation was negligible for the 3μm technology used in the design. The gm/ID methodology was used to optimize a gain boosted cascode in Ref. [5]. However, similar to [4], it suffered from the same previously mentioned drawbacks. The optimization of a three-stage nested-Miller OTA using gm/ID methodology was proposed in Ref. [8]. The design procedure aimed at optimizing both noise and settling time specifications. However, it neglected other circuit specifications, and assumed that the gm/ID values and channel lengths of all transistors are known a priori. A common shortcoming in the aforementioned works is that they do not demonstrate a fully-constrained complete design example. Lastly, it is difficult for the interested designer to replicate or apply the proposed design procedures due to the lack of details and the use of proprietary device models.

As a result, there is a need for a complete and detailed design example that clearly demonstrates the gm/ID methodology for a simple but real-life analog block, starting from a complete set of specifications and up to verification. This paper aims at providing such a design example to promote the gm/ID methodology among experienced designers who are not used to this powerful methodology, as well as novice designers who are embarking their analog IC design journey. A key merit that differentiates this work is that it clearly explains the design and optimization procedure for a complete design example using publicly available device models. Consequently, the interested reader can replicate the results, or apply the presented techniques to his own design problems. A simple single-stage OTA (also known as five-transistor OTA [10]) is used as a design example, which despite its simplicity still finds use in complex mixed-signal systems (e.g. [11]). The OTA design process is constrained by both small-signal and large-signal specifications, and is graphically illustrated using trade-off charts. The presented procedure is automated using MATLAB, and the automation program is applied to solve more sophisticated design problems. Analytical expressions for the OTA self-loading and input capacitance are derived, verified, and used in the automation program. The proposed design examples are verified using Cadence Spectre and the publicly available 180nm Predictive Technology Model (PTM) [12].

Section snippets

OTA specifications

The target design example is a single-ended output five-transistor OTA to be used as a unity-gain buffer to drive a large capacitive load. The design specifications are shown in Table 1. The available current consumption for the OTA is 20μA. In addition, a 10μA reference current is externally provided. The OTA gain-bandwidth product (GBW) is roughly equal to the buffer closed-loop bandwidth (BWCL), and the OTA common-mode input range (CMIR) is itself the buffer input range.

Trade-off charts generation

DC simulation is used

Automated design procedure using MATLAB

Section 2 showed a systematic design flow using gm/ID trade-off charts. Despite the merits of this graphical flow, it suffers from several drawbacks. First, it is time-consuming, and can be tedious if repeated several times due to the frequent changes in specifications during the initial phases of an IC design project. Second, in order to keep it tractable, the dataset was limited by choosing a relatively coarse step for channel length and ignoring second order effects, e.g., VDS dependence.

Automated optimization procedure using MATLAB

The design procedure explained in Section 2 then automated in Section 3 assumed a complete and well-defined set of specifications (constraints). However, optimizing real-life designs usually involve one or more variables that need to be maximized or minimized given a set of constraints. In this section we will give an example of such an optimization scenario within the framework presented in the previous sections.

Conclusion

A complete OTA systematic design example considering gain, bandwidth, noise, CMIR, and CMRR specifications was graphically illustrated using the gm/ID design methodology. The proposed systematic procedure was automated using MATLAB, which enabled tackling iterative and optimization problems. Analytical expressions were derived for the OTA self-loading and input capacitances. The derived expressions were further verified and employed in the automation programs. The performance of the designed

Acknowledgments

The authors would like to thank Omar A. Abu-El-ela for useful hints and discussions.

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