All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator

Abstract

This paper presents bi-directional gated delay line (BDGDL) time integrators featuring full compatibility with technology scaling, rapid integration, low power consumption, and built-in digitization, and their applications in all-digital first-order ΔΣ time-to-digital converters (TDCs). The architecture of the BDGDL time integrators, both single-ended and differential, is presented. The imperfections of the BDGDL time integrators are investigated. Two first-order ΔΣ TDCs, one with the single-ended BDGDL time integrator and the other with the differential BDGDL time integrator, are designed in an IBM 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM4 device models. The SNDR of the TDC with the differential BDGDL time integrator and a sinusoidal time input of amplitude 430 ps and frequency 231 kHz is 38 dB. The time resolution of the TDC is 6.7 ps and its power consumption is 243 μW.

Introduction

Technology scaling has resulted in the rapidly deteriorating performance of analog circuits arising mainly from shrunk voltage headroom, worsening device mismatch, and exacerbating linearity. Technology scaling, on the other hand, has sharply improved the switching time of digital circuits. Analog signal processing by means of digital circuits is highly desirable. Time-mode circuits where analog information is represented by time difference between two digital signals offer a viable and technology friendly means to combat difficulties encountered in analog signal processing. TDCs that map a time variable to a digital code are the core block of time-mode circuits and have found a broad range of applications including digital storage oscillators [1], laser range finders [2], IIR and FIR filters [3,3,4], anti-imaging filters [5], all digital frequency synthesizers [[6], [7], [8], [9], [10], [11]], multi-Gbps serial links [12], and perception systems [13], to name a few. TDCs with a high resolution, low power consumption, and a high conversion rate are essential in these applications. Improving the time resolution of sampling TDCs without an excessive silicon area and high power consumption is rather difficult as quantization noise of these TDCs is distributed uniformly across their entire spectrum [14]. TDCs that are based on gated ring oscillators, though offering an attractive first-order noise-shaping characteristic, suffer from three notable drawbacks, namely stringent phase-wrapping constraints imposed on the input [15], excessive power consumption due to the high oscillation frequency of the oscillator and the large number of the stages of the gated ring oscillator, and rigidness as noise-shaping characteristics are solely set by the GRO. ΔΣ operations are known for their ability to yield a large in-band large signal-to-noise-ratio by means of noise-shaping. ΔΣ TDCs with an analog time integrator such as charge pump time integrators, however, are not technology friendly [16,17]. In order for ΔΣ TDCs to be fully technology compatible, digitally realized time integrators whose input and output are time variables are needed. A number of all-digital time integrators emerged recently. Ali-Bakhshian and Roberts proposed a time memory cell called TLatch consisting of two switched delay units (SDUs) and capable of storing a time variable and releasing the stored time variable upon a read request [18]. A time integrator can be realized utilizing a TLatch and a pair of identical ring oscillators with SDU embedded. The output of this time integrator is upper-bound by the period of the oscillators. Not only mismatch between the oscillators and the phase accumulation of the oscillators affect the performance of the time integrator, the need for two oscillators also makes it less attractive for applications where power consumption is critical. Hong et al. proposed a time integrator whose core is a time register [10]. Time integration is realized using two time adders, one performs time addition and the other performs time registration. This time integrator, however, can only handle positive time variables. In addition, it exhibits poor linearity due to the nonlinear discharging current of the load capacitor of the time adders. The authors showed that better linearity can be achieved using a cascode time integrator [19]. Linearity can be further improved using differential cascode time integrator with the raised threshold voltage of the load inverter [20]. Time integrators constructed using a time adder and a time register suffer from two intrinsic drawbacks, namely complex timing schemes required to coordinate the operation of the time adder and time register and high power consumption due to the need for a time adder, a time register, and control logic.

This paper presents a first-order ΔΣ TDCs with BDGDL time integrators [21,22]. Since no analog component is used, the proposed time integrators are fully technology compatible. The remainder of the paper is organized as follows: Section 2 introduces BDGDLs. A single-ended BDGDL time integrator is presented. It is followed with the development of a differential BDGDL time integrator. Section 3 presents two first-order ΔΣ TDCs, one with the single-ended BDGDL time integrator and the other with the differential BDGDL time integrator. The design considerations of the BDGDL time integrators are studied in detail in Section 4. The simulation results of the TDCs are presented in Section 5. The paper is concluded in Section 6.