All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator
Introduction
Technology scaling has resulted in the rapidly deteriorating performance of analog circuits arising mainly from shrunk voltage headroom, worsening device mismatch, and exacerbating linearity. Technology scaling, on the other hand, has sharply improved the switching time of digital circuits. Analog signal processing by means of digital circuits is highly desirable. Time-mode circuits where analog information is represented by time difference between two digital signals offer a viable and technology friendly means to combat difficulties encountered in analog signal processing. TDCs that map a time variable to a digital code are the core block of time-mode circuits and have found a broad range of applications including digital storage oscillators [1], laser range finders [2], IIR and FIR filters [3,3,4], anti-imaging filters [5], all digital frequency synthesizers [[6], [7], [8], [9], [10], [11]], multi-Gbps serial links [12], and perception systems [13], to name a few. TDCs with a high resolution, low power consumption, and a high conversion rate are essential in these applications. Improving the time resolution of sampling TDCs without an excessive silicon area and high power consumption is rather difficult as quantization noise of these TDCs is distributed uniformly across their entire spectrum [14]. TDCs that are based on gated ring oscillators, though offering an attractive first-order noise-shaping characteristic, suffer from three notable drawbacks, namely stringent phase-wrapping constraints imposed on the input [15], excessive power consumption due to the high oscillation frequency of the oscillator and the large number of the stages of the gated ring oscillator, and rigidness as noise-shaping characteristics are solely set by the GRO. ΔΣ operations are known for their ability to yield a large in-band large signal-to-noise-ratio by means of noise-shaping. ΔΣ TDCs with an analog time integrator such as charge pump time integrators, however, are not technology friendly [16,17]. In order for ΔΣ TDCs to be fully technology compatible, digitally realized time integrators whose input and output are time variables are needed. A number of all-digital time integrators emerged recently. Ali-Bakhshian and Roberts proposed a time memory cell called TLatch consisting of two switched delay units (SDUs) and capable of storing a time variable and releasing the stored time variable upon a read request [18]. A time integrator can be realized utilizing a TLatch and a pair of identical ring oscillators with SDU embedded. The output of this time integrator is upper-bound by the period of the oscillators. Not only mismatch between the oscillators and the phase accumulation of the oscillators affect the performance of the time integrator, the need for two oscillators also makes it less attractive for applications where power consumption is critical. Hong et al. proposed a time integrator whose core is a time register [10]. Time integration is realized using two time adders, one performs time addition and the other performs time registration. This time integrator, however, can only handle positive time variables. In addition, it exhibits poor linearity due to the nonlinear discharging current of the load capacitor of the time adders. The authors showed that better linearity can be achieved using a cascode time integrator [19]. Linearity can be further improved using differential cascode time integrator with the raised threshold voltage of the load inverter [20]. Time integrators constructed using a time adder and a time register suffer from two intrinsic drawbacks, namely complex timing schemes required to coordinate the operation of the time adder and time register and high power consumption due to the need for a time adder, a time register, and control logic.
This paper presents a first-order ΔΣ TDCs with BDGDL time integrators [21,22]. Since no analog component is used, the proposed time integrators are fully technology compatible. The remainder of the paper is organized as follows: Section 2 introduces BDGDLs. A single-ended BDGDL time integrator is presented. It is followed with the development of a differential BDGDL time integrator. Section 3 presents two first-order ΔΣ TDCs, one with the single-ended BDGDL time integrator and the other with the differential BDGDL time integrator. The design considerations of the BDGDL time integrators are studied in detail in Section 4. The simulation results of the TDCs are presented in Section 5. The paper is concluded in Section 6.
Section snippets
Bi-directional gated delay cell
The bi-directional gated delay cell shown in Fig. 1 consists of two uni-directional gated delay stages and is capable of propagating signals in both directions. A digital signal can propagate from node 1 to node 2 (forward) if gating signal Tin > 0 or from node 2 to node 1 (backward) if Tin < 0. Consider the case where the signal propagates from node 1 to node 2. The voltage of node 1 and that of node 2 are initialized to VDD and 0 V, respectively. When Tin[k] > 0, the capacitor connected to
ΔΣ TDC with single-ended BDGDL time integrator
In this section, we utilize the single-ended BDGDL time integrator to construct a first-order ΔΣ TDC with a single-bit quantizer. Fig. 8 shows the simplified schematic of the TDC. The TDC consists of a time summer, a single-ended BDGDL time integrator, a pair of 1-of-N and DTC (digital-to-time converter) blocks, and a DFF. The output of the BDGDL time integrator is a thermometer code with the location of 0 ⇔ 1 transition determined using the 1-of-N blocks. Tin − TFB is performed using a
Design considerations
In this section, we examine a number of factors that affect the performance of the proposed TDCs. These include nonlinearity, delay mismatch, threshold mismatch, gating skew error, supply voltage noise-induced timing error, and device noise-induced timing error.
Simulation results
The ΔΣ TDCs are designed in an IBM 130 nm 1.2 V CMOS technology. The per-stage delay of the BDGDL time integrator is set to 96 ps. The input of the TDCs is a sinusoid time signal of frequency 231 kHz and amplitude 430 ps. It is generated using the differential VTC with a 25 MHz sampling clock. The TDC is analyzed using Spectre with BSIM 4 device models.
Conclusions
Two first-order ΔΣ TDCs, one with a single-ended BDGDL time integrator and the other with a differential BDGDL time integrator, were presented. The time integrators are bi-directional gated delay lines with the time variable to be integrated as the gating signal. Time integration is performed via the accumulation of the charge of the load capacitor of gated delay stages and the propagation of the logic state of the output of the gated delay stages. An attractive characteristic of the proposed
Acknowledgments
Financial support from the Natural Science and Engineering Research Council of Canada and computer-aided design tools from CMC Microsystems, Kingston, ON, Canada are gratefully acknowledged.
References (42)
- et al.
A low-cost low-power CMOS time-to-digital converter based on pulse stretching
IEEE Trans. Nucl. Sci.
(Aug. 2006) - et al.
A precise cyclic CMOS time-to-digital converter with low thermal sensitivity
IEEE Trans. Nucl. Sci.
(Aug. 2005) - et al.
K-locked-loop and its application in time mode ADC
Time-mode Circuits for Analog Computations
(2006)- et al.
Anti-imaging time-mode filter design using a PLL structure with transfer function DFT
IEEE Trans. Circ. Syst. I
(Jan. 2012) - et al.
A time-to-digital-converter-based CMOS smart temperature sensor
IEEE J. Solid State Circ.
(Aug. 2005) - et al.
A 2.1-to-2.8-GHz low-phase-noise all-digital frequency synthesizer with a time-windowed time-to-digital converter
IEEE J. Solid State Circ.
(Dec. 2010) - et al.
A low-noise wide-BW 3.6-GHz digital ΔΣ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation
IEEE J. Solid State Circ.
(Dec. 2008) - et al.
A novel wide-range delay cell for DLLs
- et al.
A 0.004 mm2 250 μW ΔΣ TDC with time-difference accumulator and a 0.012 mm2 2.5 mW bang-bang digital PLL using PRNG for low-power SoC applications
A digital PLL using oversampling delta-sigma TDC
IEEE Trans. on Circuits Syst. II
A new time-based architecture for serial communication links
A multichannel high-precision CMOS tie-to-digital converter for laser-scanner-based perception systems
IEEE Trans. Instrum. Meas.
Time-to-digital Converters
A 12-bit, 10-MHz bandwidth, continuous-time ΔΣ ADC with a 5-bit, 950-MS/s VCO-based quantizer
IEEE J. Solid State Circ.
A 71 dB dynamic range third-order ΔΣ TDC using charge pump
A 0.4-mw, 4.7-ps resolution single-loop ΔΣ TDC using a half-delay time integrator
IEEE Trans. VLSI Systems
A digital implementation of a dual-path time-to-time integrator
IEEE Trans. Circ. Syst. I
Time integrator for mixed-mode signal processing
1-1 MASH delta-sigma time-to-digital converter with differential cascode time integrator
Low-power all-digital delta-sigma TDC with bi-directional gated delay line time integrator
Cited by (6)
Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter
2022, Microelectronics JournalTime-to-digital converters—A comprehensive review
2021, International Journal of Circuit Theory and ApplicationsPerformance evaluation of measured time stretching approach for event timer
2021, Proceedings of the 9th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2021All-digital power-efficient integrating frequency difference-to-digital converter for GHz frequency-locking
2020, IET Circuits, Devices and SystemsAll-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line
2020, Midwest Symposium on Circuits and SystemsTime-based all-digital ΔΣ time-to-digital converter with pre-skewed bi-directional gated delay line time integrator
2020, IET Circuits, Devices and Systems