A 10-bit 100-MS/s 5.23-mW SAR ADC in 0.18-μm CMOS
Introduction
Nowadays, successive-approximation (SAR) ADC has drawn a lot of attentions due to its wide usage in many special fields, such as portable electronic systems and wireless sensor networks. Compared with other types ADC, SAR ADCs exhibit the best energy efficiency for medium-to-high speed, moderate-resolution, low-power applications [1,2,17] since the process scaling down. However, it is still difficult to compromise between the speed, resolution and power of SAR ADCs. Increasing speed will cause the decision errors of SAR ADCs which deteriorates the resolution performance. Moreover, the energy per conversion of SAR ADCs is approximately linearly proportional to the resolutions, and when speed is close to upper limit, the power consumption will be greatly increased [3]. Therefore, it is an austere challenge to achieve an appropriate compromise between the specifications of SAR ADC in various applications.
In this paper, a single-channel, single-bit/cycle SAR ADC is designed to boost the conversion rate while maintaining attractive power efficiency. A novel switching scheme based on split-capacitor VCM-based switching is proposed to achieve this goal. The MSB and 2nd-MSB capacitors in digital to analog convertor (DAC) are charged (or discharged) by VREF (or Gnd) instead of VCM, improving the DAC settling speed. In addition, asynchronous clock as well as dynamic SAR logic controller is employed to further increase the conversion speed. The measurement results show that a 10-bit 100 MS/s SAR ADC adopting the proposed techniques achieves a Walden figure of merit (FoM) of 123.2 fJ/conversion step, which is comparable to the state-of-the- art in 0.18 μm CMOS process.
This paper is organized as follows. Section 2 describes the overall ADC architecture. Section 3 presents the proposed switching scheme. In addition, the average switching energy is also analyzed in this section. Section 4 introduces the circuit details including the optimizations of the bootstrapped switch, the comparator and the SAR logic. Section 5 shows the measurement results of the prototype SAR ADC. And section 6 concludes this paper.
Section snippets
ADC architecture
Fig. 1 shows the structure of the proposed SAR ADC. In general, it consists of two bootstrapped sampling switches, a differential binary-weighted capacitive DAC, a lower-power dynamic comparator, an asynchronous SAR logic controller and a clock generator. To suppress the supply voltage noise and have good common-mode noise rejection, the fully differential architecture is employed. The input signal is sampled on the top-plate nodes of the capacitor array by bootstrapped switches, and the
Modified spilt-capacitor VCM-based switching scheme
Compared with the conventional switching scheme, the energy-saving [5], monotonic [6] and VCM-based [7] switching schemes reduce switching energy by 69%, 81% and 90%, respectively. Although VCM-based switching scheme could save power consumption, it is difficult for the CMOS transmission gate to transfer the VCM voltage exactly in a short-time. As a result, the incomplete settling deteriorates the ADC performance [8]. In order to make the proposed SAR ADC achieves the performance of 10-bit
Bootstrapped switch
Bootstrapped switch is the elementary block in SAR ADC, which could enhance the sampling linearity. One factor affecting sampling linearity is the on-resistance variation of switching transistor. VGS in bootstrapped switches is maintained when VIN changes, thus the transistor's on-resistance (Ron) is stable, improving the linearity of sampling switches. The other factor deteriorating sampling linearity is the charge injection of switching transistor. As shown in Fig. 7, transistor MP is used
Measurement results
By employing the proposed switching scheme and optimized SAR logic controller, a 10-bit 100 MS/s SAR ADC is fabricated in SMIC 0.18-μm 1P6M CMOS process. The total capacitance of sample and hold circuit is 8.192 pF implemented by metal-isolator-metal (MIM) capacitors. And the unit capacitance is about 16 fF. The on-chip decoupling capacitance for VREF and VCM are about 345 pF and 315 pF, respectively. The decoupling capacitors are located surround the core area for reducing the reference
Conclusion
This paper presents a 10-bit 100 MS/s single-channel SAR ADC. To achieve higher conversion rate and lower power consumption, the proposed SAR ADC employs a modified capacitance-split VCM-based switching scheme with decreased total capacitors and asynchronous technique. The proposed SAR ADC has been fabricated using SMIC 0.18 μm 1P6M CMOS process with MIM capacitor option, and the total capacitance of sample and hold circuit is 8.192 pF with its unit capacitance being about 16 fF. The
Acknowledgments
This work was supported by the National Natural Science Foundation of China (61625403, 61674118).
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