Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects
Introduction
Repeaterless low swing interconnects need clock retiming circuits at the receiver for sampling the low swing data at the appropriate time instant [1]. In the case of on-chip interconnects, the clock for the transmitter and the receiver is derived from the same clock generating PLL. Hence, the frequency of the clock at the transmitter and at the receiver is equal. However, due to high latency of long interconnects the phase relationship between the data and the (local) clock at the receiver is arbitrary [2]. Conventional repeater inserted interconnects are implemented in multi-cycle synchronous fashion with periodic flip-flops [3]. However, such techniques cannot be used for repeaterless low swing interconnects without compromizing some of its advantages. Hence, clock retiming circuits are needed at the receivers of low swing interconnects for correcting the phase of the receiver's clock. Such retiming circuits, wherein only phase correction is done on a clock of the correct frequency, are known as mesochronous clock retiming circuits.
Though mesochronous clock retiming circuits ideally have a clock of the exact frequency available and only perform phase corrections, they are influenced by different types of jitter in the clock. For example, drift in the frequency of the clock generating PLL appears as common mode to the transmitter and receiver. Jitter in the data due to inter-symbol interference and random noise results in uncorrelated jitter between the data and the clock at the receiver. The effect of jitter in clock retiming circuits has been extensively studied for off-chip links [4]. However, the effect of jitter on clock retiming circuits of on-chip interconnects has not received much attention. For on-chip interconnects, uncorrelated jitter can sometimes result in a retiming circuit taking too long to converge as well [5].
In this paper, we analyze the effect of different types of jitter on the coarse + fine type clock retiming circuit which we had reported earlier [6]. With supporting measured results obtained from a chip fabricated in UMC 130 nm CMOS technology, we validate the robustness of this circuit. The next section gives a brief introduction to the coarse + fine clock retiming circuit.
Section snippets
Clock retiming circuit
Fig. 1 shows a block diagram of the coarse + fine clock retiming circuit [6]. It consists of a fine tuning loop and a coarse tuning loop. The main component of the fine tuning loop is a voltage controlled delay line (VCDL) that provides a controllable delay to the clock. The main component of the coarse tuning loop is a delay locked loop (DLL) that generates multiple phases of the clock. Operation of the circuit starts with the fine tuning loop trying to get the clock to the center of the data
Experiments
Fig. 5 shows a photograph of a bare die of the fabricated chip. The chip was tested with Centellax TG1B1-A BER tester [7] and Centellax TG1C1-A clock synthesizer [8]. As mentioned earlier, a low swing transmitter with a short interconnect is used to generate the data input for testing the clock retiming circuit. The clock synthesizer instrument has 6 outputs, among which the phase of 1 clock signal can be adjusted relative to the others. The clock with adjustable phase is used as the source for
Conclusion
This paper discusses and demonstrates the effect of different types of jitter on the performance of the coarse + fine type clock retiming circuit for on-chip interconnects. We first discuss the design of the retiming circuit to ensure correct operation across process corners. With the aid of measured results obtained from a chip fabricated in UMC 130 nm technology we demonstrate its robustness to correlated and uncorrelated jitter in the clock. We also demonstrate how jitter can result in
Acknowledgments
The authors thank Nagendra Krishnapura and Shanthi Pavan of IIT Madras for discussions during chip testing, and for giving access to the VLSI Testing lab of IIT Madras. This work was supported by the Tata Consultancy Services (TCS) and the SMDP programme by Meity, Government of India, in the form of student scholarships and CAD tool licenses respectively. The test chip was fabricated through the mini@sic MPW program of Europractice. Free samples provided by Texas Instruments were used for the
References (11)
- et al.
Current-mode transceiver for silicon interposer channel
IEEE J. Solid State Circ.
(2014) - et al.
Power efficient gigabit communication over capacitively driven RC-limited on-chip interconnects
IEEE J. Solid State Circ.
(2010) - et al.
Flip-flop and repeater insertion for early interconnect planning
- et al.
A 9.6-Gb/s 1.22-mW/Gb/s data-jitter mixing forwarded-clock receiver in 65-nm CMOS
IEEE Trans. Very Large Scale Integr. Syst.
(2015) - et al.
Settling time of mesochronous clock re-timing circuits in the presence of timing jitter