1.15 GHz image rejection filter with 45 dB image rejection ratio and 8.4 mW DC power in 90 nm CMOS

doi:10.1016/j.mejo.2018.12.003

Microelectronics Journal

Volume 84, February 2019, Pages 48-53

https://doi.org/10.1016/j.mejo.2018.12.003 Get rights and content

Abstract

A 1.15 GHz image rejection filter in 90 nm CMOS is presented. It consists of two band-pass filter stages and one band-stop filter stage, with the Q-enhancing and frequency stagger-tuning techniques to compensate the loss of low quality factor on-chip passive components and maintain enough bandwidth, respectively. The presented filter has been integrated in one K-band dual down-conversion super-heterodyne receiver and achieves 45 dB image rejection ratio at 140 MHz offset with >22 MHz signal bandwidth. The DC power consumption is 8.4 mW.

Introduction

Monolithic receiver generally adopts zero-IF architectures due to its simplicity, flexibility and high integration level. However, due to the non-idealities including poor 2^nd-order non-linearity, dc-offset, $1 / f$ noise, I/Q mismatching, the zero-IF receiver only achieves limited sensitivity and could not be used in high-sensitivity communications. On the contrary, thanks to high sensitivity, selectivity and higher intermediate frequency (IF), super-heterodyne receiver is widely used in satellite communications and radar systems without considering the above problems [1].

Compared with the traditional single down-conversion super-heterodyne architecture, dual down-conversion architecture is attractive to realize highly integrated array receivers as it is easier to achieve high image rejection ratio. Although the zero-IF or image-rejection mixing architecture [2] could be used to implement the second down-conversion with relaxed image rejection (IR) specification, the fixed IF frequency (70 MHz in this work) required by the digital baseband or the severe trade-off between loss, IRR and bandwidth doesn't allow to use them. Therefore, this work still uses the super-heterodyne conversion to implement the second down-conversion and one high performance image rejection filter should be integrated before this conversion. In this receiver architecture (Fig. 1), target signal (22.55 GHz-23.55 GHz in this work) is amplified by the low noise amplifier (LNA) and mixed with the first local oscillator (LO) (21.4 GHz–22.4 GHz in this work) to produce a fixed intermediate frequency (IF) (1.15 GHz). Then, it is amplified by the image rejection filter and mixed with the second LO (1.08 GHz) to generate the fixed 70 MHz baseband signal. Finally, the signal is sent out through the baseband band-pass filter (BPF) and automatic gain control amplifier (AGC). The first IF frequency is usually high (∼GHz), which makes the first image signal in the first down-conversion far away from the useful signals and significantly relaxes the image rejection requirement on the first down-conversion. However, enough image rejection ratio has to be achieved before the second down-conversion, which is usually realized with an off-chip SAW filter, resulting in high cost and low integration level [3]. Therefore, the monolithic integration scheme with the on-chip image rejection filter is more attractive. However, it is challenging to realize high performance image rejection filter in CMOS since the pass-band frequency is up to ∼ GHz (1.15 GHz in this work) and the image interferences locate only ∼100 MHz offset (140 MHz in this work). Wide signal bandwidth requirement (22 MHz) significantly increases the design challenge due to the trade-off between the bandwidth and the image rejection ratio.

The on-chip image rejection filter usually employs the band-pass or band-stop filtering characteristics of the LC resonant network to provide the image rejection capability. However, the achievable image rejection ratio is limited due to low quality factor (Q) passive components (mainly the inductors) in CMOS process. Techniques to improve the quality factor of the on-chip spiral inductors are presented in Refs. [4,5], where the cross-coupled pairs are used to provide negative resistance and compensate the loss of the passive components. However, the bandwidth has to be traded-off since the higher Q results in narrower bandwidth. Refs [6,7] adopt negative resistance to compensate the loss of the transformer and realize wide bandwidth, but the transformer brings higher insertion loss, resulting in low gain and high power consumption. Frequency stagger-tuning technique is widely used to obtain wide bandwidth in broadband applications [8].

The main contributions of this paper are summarized as follows.

1)
The 1.15 GHz on-chip image rejection filter is realized in 90 nm CMOS, which has been integrated in one K-band dual-down receiver and achieves 45 dB image rejection ratio at 140 MHz offset with >22 MHz signal bandwidth, greatly improves the integration compared with traditional super-heterodyne receiver.
2)
The proposed image rejection filter considers the bandwidth, selectivity, and image rejection ratio. The Q-enhancing technique based on the negative resistance compensation is used to compensate the loss of the on-chip passive components and improve the image rejection ratio, and the frequency stagger-tuning technique is utilized to mitigate the bandwidth loss and achieves balanced performance among low power, flat gain and good image rejection ratio.

The paper is organized as follows. Section 2 introduces the circuit design. In Section 3, the measurement results are shown. Section 4 presents the conclusions.

Section snippets

Q-enhancing technique and frequency stagger-tuning technique

As shown in Fig. 2(a), a negative resistance is introduced in the LC tank by the cross-coupled pair. The negative resistance of the crossed pair can be written as $- \frac{2}{g_{m}}$ , where $g_{m}$ is the transconductance of the cross-coupled transistor $M_{1}$ , so the equivalent parallel resistance of the LC resonant tank could be calculated as follows: $R_{p}^{'} = \frac{R_{p}}{1 - g_{m} \frac{R_{p}}{2}}$

Where $R_{p}$ is the inherent equivalent parallel resistance of the LC resonant tank, Fig. 2 (b) shows the calculated $R_{p}^{'}$ versus $g_{m}$ . $g_{m} = \frac{2}{R_{p}}$ is the point where $R_{p}^{'}$ is

Measurement results

The presented image rejection filter has been implemented in 90 nm CMOS. Fig. 8 shows its microphotograph, and the core chip area is $1221.27 u m \times 518.47 u m$ . The filter has been integrated into one dual down-conversion receiver and it itself consumes $8.4 m W$ DC power from a 1.2 V power supply. BGR and SPI in Fig. 8 provide the reference current and digital control codes for the filter, respectively.

The measurements are performed with the on-wafer probing. The prober is connected to the signal generator,

Conclusion

In this paper, a 1.15 GHz image rejection filter in 90 nm CMOS is presented. It consists of two band-pass filter stages and one band-stop filter stage. The Q-enhancing technique based on the negative resistance compensation is used to compensate the loss of the on-chip passive components and improve the image rejection ratio, and the frequency stagger-tuning technique is utilized to mitigate the bandwidth loss and achieve balanced performance among low power, flat gain and good image rejection.

Acknowledgments

This work is supported in part by the National Natural Science Foundation of China (No. 61774093).

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There are more references available in the full text version of this article.

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1.15 GHz image rejection filter with 45 dB image rejection ratio and 8.4 mW DC power in 90 nm CMOS

Abstract

Introduction

Section snippets

Q-enhancing technique and frequency stagger-tuning technique

Measurement results

Conclusion

Acknowledgments

Electron. Lett.

A low-power process-scalable super-heterodyne receiver with integrated high-Q filters

IEEE J. Solid State Circ.

CMOS mixers and polyphase filters for large image rejection

IEEE J. Solid State Circ.

A +78 dBm IIP2 CMOS direct down conversion mixer for fully integrated UMTS receivers

IEEE J. Solid State Circ.

A new Q-enhancement architecture for saw-less communication receiver in 65-nm CMOS

2 GHz automatically tuned Q-enhanced CMOS bandpass filter

1.15 GHz image rejection filter with 45 dB image rejection ratio and 8.4 mW DC power in 90 nm CMOS