Design and analysis of dynamically configurable electrostatic doped carbon nanotube tunnel FET
Introduction
In recent years, carbon nanotubes (CNs) become a good replacement for channel material in metal oxide semiconductor field effect transistor (MOSFET) due to their good electrical properties. CNs do not suffer from mobility degradation [1] and can be used under sub-10-nm era, as nanotubes are capable of maintaining characteristics with low OFF currents (IOFF) similar to long channel type MOSFET [2]. Carbon nanotube field effect transistor (CNFET) can be further of two types: Schottky barrier CNFET and conventional CNFET based on the choice of CNT and the type of contacts made with source and drain sides. However, a new concept of carbon nanotube tunnel FET (CN-TFET) emerges in recent years [3]. CN-TFET gives superior results over conventional CNFET in terms of IOFF and steep subthreshold swing (SS) [4,5]. However ambipolar currents are observed in CN-TFET due to band to band tunneling. For suppressing ambipolar currents, a novel barrier controlled tunnel FET [6] was proposed which consists of triple gate material with different work functions. Although silicon based tunnel FET (TFET) also gives excellent results in terms of ION/IOFF ratio and SS [7] but CN-TFET exhibits various advantages. Some of the important advantages are aggressive channel length scaling due to absence of mobility degradation [8]; variable bandgap with single material [9]; ultra thin body device that is possible due to smaller diameter (1–3 nm) [10]; and compatibility of CNT with high-K materials [11] resulting in high ON current [12].
Since doping CNs is difficult due to non applicability of conventional doping techniques [13] which makes fabrication process costly and complex. In lieu of this, dopingless CN based designs are being explored which will reduce process complexity. The dopingless technique based on charge plasma was first proposed for the p-n diode [14] and subsequently it was implemented for bipolar transistor [15]. Charge plasma technique is based on the fact that doping is created by work function of electrodes at source and drain sides. Charge plasma technique has also been implemented in MOSFET [16] and tunnel FET [17,18]. However, one limitation of charge plasma technique is that doping is static in this case. To overcome this limitation, electrostatic doping based CNFET [19] was fabricated which showed excellent unipolar characteristics. Electrostatic doping introduced with help of polarity gates (PGs) at source and drain sides which provides additional benefit of dynamic configuration that allows same device to be used as n-type and p-type by reversing bias at PGs. Recently electrostatic doped CNFET is modeled for circuit application [20] and its analysis demonstrated that electrostatic doped CNFET is suitable for low power circuit applications [21,22]. Also dynamic configuration has been introduced in silicon based FETs by varying bias at PGs on source and drain regions [23,24]. In this work, a novel design of dopingless CN-TFET is proposed with dynamically configurable feature. The device is named as electrostatic doped CN-TFET (ED CN-TFET) in which doped source and drain regions are achieved through applying opposite bias at PGs.
The proposed ED CN-TFET is designed and simulated in NanoTCAD ViDES [25] and compared with the conventional CN-TFET and it has been found that ED CN-TFET gives better SS and less IOFF. The most important parameter which affects the performance of CN-TFET is diameter of CNT. Since bandgap is inversely proportional to diameter, hence proper selection of diameter ensures good OFF state. Also, PG bias modulates carrier concentration which effects band profile in source and drain sides. Therefore, proper selection of PG bias ensures proper OFF state. Appropriate values of diameter and PG bias are required for proper ON-OFF ratio. The values are decided through extensive simulations at different bias and diameters.
Section snippets
Device structure and simulation parameters
The structure used for the simulation purpose is planar double gate CN-TFET. Fig. 1(a) shows the 2-dimensinal cross sectional view of conventional CN-TFET and simulation parameters are adapted from Ref. [2] as: diameter (d) = 1 nm for (13,0) zigzag CNT, equivalent oxide thickness (EOT) = 1 nm, channel length (L) = 20 nm and gate metal work function = 4.1eV. The doping concentrations used are 5E-03 M fraction [25] for n-type and -5E-03 M fraction (MF) for p-type regions.
Fig. 2(a) shows
Simulation results and discussions
In the proposed ED CN-TFET, p+ and n+ regions are achieved through appropriate bias on PGs. As a result of this bias, carrier concentration is achieved on source and drain regions. Fig. 4 shows band diagram of proposed ED CN-TFET where bands are shifted with action of PGs biases i.e. VPG-1 = −0.75 V and VPG-2 = 0.75 V. OFF and ON states are shown with action of gate bias as VG = 0 V and VG = 1 V respectively. It can be observed from Fig. 4 that tunneling width is equal to SGAP,S which is small
Sensitivity analysis
The device is sensitive to the EOT which is another important parameter in MOSFET. EOT also plays important role in scaled down device as it leads to oxide capacitance which is used to evaluate quantum capacitance limit. Fig. 18 shows the effect of EOT on IDS-VGS characteristics. It can be inferred from the results that both conventional and proposed device follow same trend of increase in ION as EOT reduces. However, due to low-k dielectric material (SiO2), there will be poor isolation between
Conclusion
A novel design of dynamically configurable electrostatic doped carbon nanotube tunnel FET (ED CN-TFET) is proposed. ED CN-TFET reduced thermal budget and process complexity over conventional CN-TFET by removing doping process. The proposed device reduces ambipolar currents with additional advantage of dynamic reconfiguration which gives symmetric p-type characteristics making the proposed device suitable for circuit applications. Also, 3-D simulations have been performed for proposed ED CN-TFET
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