Design and FPGA implementation of lattice wave fractional order digital differentiator

Abstract

This paper deals with the design and FPGA implementation of a fractional order digital differentiator. It is realized using computationally efficient lattice wave digital filter (LWDF) which requires minimum multipliers in comparison to the direct form structure. A nature inspired ant lion optimization (ALO) algorithm is utilized to compute optimal coefficients of the LWDF based digital differentiator. The proposed LWDF based digital differentiator is compared with the existing literature in terms of magnitude response, percentage magnitude error and root mean square magnitude error. LWDF structure comprises of constant coefficient multipliers, adders and delay units which are implemented on FPGA with the help of Xilinx system generator for DSP design tool. For efficient implementation of multipliers, multiplier-less logic through digit recoding techniques such as canonic signed digit (CSD) representation and radix-2^r encoding are described through Verilog HDL and incorporated in the implementation model as black box. Post-implementation results show that implementation based on the radix-2^r encoding is found to be more efficient than that of the CSD encoding. The design and implementation results are also reported to highlight the improvements.

Introduction

In signal processing, situation often arises which needs to evaluate time derivative of a given signal. For instance, in order to extract ECG feature signal for QRS complex detection, derivative based preprocessing is employed [1]. Geometrical properties and contrast resolution of an image is enhanced using fractional order differentiator [2]. A dynamical system can be characterized through differential equations of integer order, however it is exhibited that dynamical systems are better modelled using arbitrary order operators [3]. The fractional derivative operator of order a for a function f(x) is $D^{a}f\left(x\right)=\frac{d^{a}f\left(x\right)}{d{x}^a}$. Fractional order differentiators are employed to evaluate the derivative operator D^a in continuous or discrete-time domain. Since digital techniques have more often proved to be advantageous compared to its analog counterpart, efficient design and implementation of fractional order digital differentiator has been an attractive problem for researchers [1,[4], [5], [6], [7], [8], [9], [10]].

The transfer function of fractional order differentiator (FOD) is given by

$$H_{FOD}\left(s\right)=s^r$$

where r denotes a positive real number lies in the range [0, 1] [11]. FOD is an infinite dimensional system, hence to implement it in digital domain, it must be approximated with finite dimensional transfer function which is often referred to as FOD discretization problem [12,13]. It can be classified into two general types as direct and indirect discretization methods. Existing literature on direct discretization include the application of the direct power series expansion of the Euler operator [14], the continued fraction expansion of the Tustin operator [13], the numerical integration methods [15], Al-Alaoui operator which results from combination of Euler and Tustin operator [[16], [17], [18]]. In case of indirect discretization, continuous-time frequency domain fitting followed by mapping of s to z operator is performed [[19], [20], [21]]. A survey of differentiator and integrator obtained using both the method is given in Refs. [22,23]. Most of these discretization methods have been applied in infinite impulse response (IIR) system, however, finite impulse response (FIR) system can also be used to design digital differentiator as demonstrated in Refs. [4,5,[24], [25], [26]]. Recent literature reveals that the FOD design requirement can be structured as an optimization problem in terms of an error function which needs to be minimized utilizing optimization algorithms. Gupta et al. proposed FOD models by employing particle swarm optimization (PSO), genetic algorithm (GA), and PSO-GA hybrid optimization for enhancing digital differential operator [9]. Cuckoo search algorithm (CSA) is used to obtain coefficients of finite impulse response based FOD [4]. Flower pollination algorithm was used to design FOD as IIR system [10]. Nature inspired bat algorithm was employed in Ref. [8] to design FOD for frequencies in microwave range. Mahata et al. used adaptive Gbest-guided gravitational search algorithm for designing fractional order digital differentiator in Ref. [27].

After the design phase, system function obtained as difference equation of the form FIR or IIR can be realized by several equivalent structures. Choice of structure depends upon computational complexity, memory requirement and data representation [28]. Direct-form realization of an IIR system requires M + N − 1 multipliers and M + N − 2 adders where M and N − 1 represent number of coefficients in numerator and denominator of the transfer function, respectively. Moreover, IIR system coefficients are sensitive to quantization and round-off errors which makes their implementation complex. To address these issues wave digital filter (WDF) can be employed for implementing FOD. WDF can handle finite word length effect with minimum number of multiplication operation [29]. WDFs are derived from classical filter networks presented by Fettweis [30]. WDFs exhibit properties such as reduced accuracy requirement for multiplier coefficient and good stability under finite arithmetic conditions. WDF in lattice configuration referred as lattice wave digital filter was used to design comb filter [31], Hilbert transformer [32], and lowpass and highpass filters [33].

Hardware implementation of signal processing system such as FOD can be done through application specific integrated circuit (ASIC), programmable digital signal processor (PDSP) or FPGA. In recent years, DSP market is dominated by FPGA based design due to its several advantages. FPGA exploits parallelism, reconfigurability, low non-recurring engineering (NRE) cost, and fast time to market [34]. Jiang et al. realized the fractional operator as IIR system and FIR system [35]. IIR realization is then implemented on FPGA as parallel combination of first order filters using the in-built FPGA multipliers. The FIR approximation of the fractional operator is implemented on the FPGA employing pipelined multiplierless architecture. The work is then extended in Ref. [36], where, a method for implementing general fractional order transfer function on FPGA is proposed. Fractional order derivatives and integrals are implemented as fixed point structures which are then used as building blocks for developing fractional order system. Rana et al. proposed a systematic procedure for implementing the fractional integrator and differentiator using Grünwald–Letnikov (GL) definition on FPGA through LabVIEW design environment [37]. FPGA implementation of fractional integral and derivatives based on GL definition is also presented in Ref. [38]. Most recently, fixed window and linear approximation method are considered for FPGA implementation of fractional order integrator and differentiator [39].

Efficiency of FPGA based systems is governed by two key principles: number representation and implementation of basic algebraic operation. This is due to the fact that FPGA possesses bit level programming architecture. If high dynamic range of data is not required then fixed point representation is preferred over floating point as it offers higher speed with lower hardware cost. Basic computation units required for realization of DSP systems including FOD are multiplication and addition. Complexity of multipliers can be minimized if one of the operands is a constant which is the case in most DSP systems. Multiplication with one of the two operands being a constant is also known as scaling operation which can be converted to addition and/or subtraction and bit shifting problem commonly known as single constant multiplication (SCM). Various methods have been proposed in the literature for efficient implementation of SCM which includes digit recoding algorithms such as canonical signed digit representation [40], Booth recoding algorithm [41] and common subexpression elimination techniques [[42], [43], [44]].

The purpose of this paper is to first design fractional order digital differentiator by transforming the transfer function of an ideal and actual FOD into an error function which is then minimized by using nature inspired optimization algorithm. If the FOD is realized in direct-form II structure, it requires 2N + 1 coefficients for an N^th order IIR filter. Whereas, lattice wave digital filter based structure requires N number of γ coefficients for N^th order filter. Hence, lattice wave digital filter is considered as the actual FOD. Optimal γ coefficients are determined using ant lion optimization algorithm to approximate ideal transfer function of FOD. Secondly, values of γ coefficients so obtained in the design phase are utilized for fixed point FPGA implementation. To the best of author's knowledge no literature were found implementing lattice wave digital filter based FOD on FPGA. Lattice wave digital filters are constructed using symmetric two port adaptors and delay units, moreover, each adaptor is a network of adders and constant multipliers. Device utilization and latency are minimized by employing multiplier-less operation through multi-bit recoding technique based on CSD and radix-2^r arithmetic. Time domain input-output waveforms are also observed through hardware co-simulation with system generator for DSP on target Xilinx Virtex-7 FPGA.

This paper is organised as follows: Design steps for digital fractional order differentiator are discussed along with the review of lattice wave digital filter and the applied optimization algorithm in Section 2. Section 3 is dedicated for FPGA implementation of the designed LWDF based FOD through system generator for DSP with emphasis on reducing resourse utilization by digit recoding techniques for efficient implementation of single constant multiplication. Conclusion is presented in Section 4.