Elsevier

Microelectronics Journal

Volume 92, October 2019, 104603
Microelectronics Journal

A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology

https://doi.org/10.1016/j.mejo.2019.104603Get rights and content

Abstract

The demand for high-performance analog-to-digital converters is pushing toward the utilization of small dynamic comparators with low power consumption, low offset voltage, high speed, and independent input common-mode voltage. In this paper, a new high-speed dynamic comparator is presented, which its delay time is decreased compared to conventional dynamic comparators. In the suggested comparator, a complementary differential pair is utilized in the input to improve the offset voltage and comparison speed. The equations related to the delay time and input referred offset voltage of the proposed structure are derived, and the effective parameters to reduce them are identified. The post-layout simulation results in 65 nm CMOS technology demonstrate that the clock frequency of the proposed comparator can be 6 GHz while the delay time is 42.7 ps. The power consumption is 381 μW when the proposed comparator is supplied with 1.2 V. Also, the occupied area is 141.7 μm2.

Introduction

Due to the increased usage of analog-to-digital converters (ADCs) in a variety of systems such as wireless communications, video systems, Ethernet, and health-care, therefore, ADCs need to be optimized for the trade-off between power consumption, high-resolution, and high-speed operation [[1], [2], [3], [4], [5]]. On the other hand, specifications of mixed-mode circuits (analog-digital) heavily depend on the use of technology. With scaling down of CMOS technologies, supply voltage and the input voltage full-scale range decrease while the threshold voltage of the transistors is not scaled down at the same rate as the technology. Moreover, mismatch and process variations increase by dwindling feature size when devices are also scaled down. These trends make mixed-mode circuits design more challenging. One of the critical mixed-mode parts of an ADC greatly affected by transistor dimension scaling is a comparator. In the design of a comparator, many aspects of the performance parameters such as input-referred offset voltage, voltage gain, kickback noise, linearity, overdrive-recovery, speed, supply voltage, and common-mode voltage level are important along with power consumption [[6], [7], [8], [9]]. These characteristics of comparators also play the dominant role in ADC architectures like Flash, Pipe-line and SAR ADC [2,4,5]. The trade-off between these characteristics is of the main challenges of designers.

Nowadays, the emphasis has been given towards the design of low-power high-speed low-offset comparator with independent common-mode voltage [[6], [7], [8], [9]]. So, static comparators are rarely used in any ADC structure due to their speed limitations and high power consumption [10]. For high-speed operation with relatively low offset and power consumption, dynamic comparators seem to be a suitable solution. However, common-mode voltage level dependency and kickback noise are major concerns. In other words, The most important advantage of these comparators is their power efficiency since they do not use a preamplifier, but the input offset voltage of these comparators is high and has a strong dependency on the variations of the common-mode voltage level [6,8]. Recently, many attempts to achieve high-speed and low-offset with low-power consumption dynamic comparators are available in the literature. A three-phase dynamic comparator is presented in Ref. [7], which utilizes a delayed clock signal to decouple the trade-off between power consumption and speed. By using this delayed clock signal, the preamplifier gain increases which leads to reducing the delay of the latch circuit and improve the offset voltage. However, the comparator suffers from kickback noise and common-mode voltage dependency. In Ref. [11], in order to achieve a higher speed and having a lower power consumption, a diode-connected transistor is utilized as a voltage limiter. Consequently, by the mentioned transistor, the latch stage potency of the drive is boosted which leads to increasing the speed. As regards, the specifications of the comparator is dependent on the input common-mode voltage. Furthermore, to alleviate the offset voltage, larger input transistors are used which result in increased power consumption. In Ref. [12], a high-speed comparator is presented that its preamplifier and latch stages are combined to improve the speed and chip area at the cost of offset voltage and power consumption. Also, the proposed comparator suffers from a dependency on the input common-mode voltage level. In Ref. [13], a single-stage dynamic comparator with a new clock pattern is presented. By using this clock pattern, offset voltage is improved, and the comparator achieves to a higher speed. In Ref. [8], the proposed dynamic comparator uses a shared charge reset switch to provide a higher-speed comparison. Also, before the comparison, by using this reset switch, output nodes are equalized, and overdrive recovery is provided. However, the limited gain of the preamplifier affects the comparison speed. Moreover, the comparator suffers from offset voltage and common-mode voltage dependency.

This paper presents a new high-speed low-power dynamic comparator. The proposed comparator which uses a complementary differential amplifier combined with a latch is benefited from a 3-phase clock pattern to decrease the delay time and improve the offset voltage. Also, by utilizing an NMOS switch between the output nodes of the comparator based on the concept of shared charge in the reset phase, the delay time is reduced. Moreover, equations related to lower the delay time and offset voltage are derived.

The rest of this paper is organized as follows: Section 2 presents the proposed dynamic comparator, followed by analytical derivations of the delay time and offset voltage in section 3. The simulation results are explained in section 4 and finally, the paper is concluded in section 5.

Section snippets

Proposed dynamic comparator

The proposed dynamic comparator utilizes a complementary differential amplifier combined with a latch as is depicted in Fig. 1(a). Therefore, the gain of this comparator will be high due to using the complementary differential amplifier, which leads to improving the delay time. The comparator works with three control signals, as shown in Fig. 1(b), to enhance the comparison speed. To reduce the delay time, and remove the memory effect inside the latch, the output nodes should be equalized to a

Analytical derivation

To identify the main contributors to reduce the delay time and offset voltage of the proposed comparator, an analysis of the delay and offset of the proposed structure is presented. Also, the noise behavior of the proposed comparator is studied.

Simulation results

In order to verify the performance of the proposed circuit, the proposed comparator is simulated in 65 nm CMOS technology with a 1.2 V power supply. The layout of the proposed dynamic comparator is depicted in Fig. 8, which occupies the area of 141.7 μm2 (10.9 μm×13 μm). By choosing the appropriate place of the elements and mirroring half of the circuit in the layout, the maximum symmetry is provided.

Table 1 shows the values of the utilized components of the proposed comparator.

Fig. 9 shows the

Conclusion

In this paper, a new high-speed low-power dynamic comparator was presented. In the proposed comparator, to reduce the delay, the outputs nodes were equalized near toVdd/2before making a comparison. Also, in the input stage, to decrease the delay and improve the input referred offset voltage, a complementary differential pair was utilized. Moreover, by using this complementary differential pair, the proposed dynamic comparator has less dependency on common-mode voltage variations. Furthermore,

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