Elsevier

Microelectronics Journal

Volume 95, January 2020, 104660
Microelectronics Journal

A high PSRR bandgap voltage reference with piecewise compensation

https://doi.org/10.1016/j.mejo.2019.104660Get rights and content

Abstract

This paper describes an alternative high power supply rejection ratio (PSRR) bandgap voltage reference (BGR) circuit with piecewise compensation. A proportional to absolute temperature (PTAT) current structure with high loop gain is adopted to achieve high PSRR, a current proportional to absolute temperature square (PTAT2) circuit is used to implement the temperature piecewise compensate. Experimental results of the proposed BGR implemented in a 0.5 ​μm CMOS process demonstrate that a PSRR of 83 ​dB is achieved, and a temperature coefficient (TC) of 8.83 ​ppm/°C over a temperature range of 165 ​°C (−40 ​°C–125 ​°C) is realized.

Introduction

Bandgap voltage references (BGR) are widely applied in analog and mixed-signal integrated circuits, such as AD converters, power converters and flash memories. The performance of these circuits depends directly on the BGR characteristics, i.e. temperature coefficient (TC), power supply reject ratio (PSRR), temperature range (TR), accuracy, power consumption, etc. Widlar [1] and Brokaw [2] proposed first-order temperature compensated conventional BGR circuit in 1970s. With regard to the nonlinearity of voltage VBE, the TC of first-order temperature compensated references is always limited to 10–100 ​ppm/°C [[3], [4], [5], [6]]. In order to overcome the limitation, many high-order temperature compensation approaches have been developed [3,[7], [8], [9]]. The TC of those curvature compensated BGRs by using piecewise current in Refs. [3,7] achieved less than 10 ​ppm/°C, but they had low PSRR. The main techniques to enhance PSRR are cascode structures [10] and pre-regulated supply voltage [11]. However, how to generate the high swing bias voltage for cascode structures while still minimizing the power consumption and the supply voltage is a challenge. Similarly, the pre-regulated technology also increases the demand for power supply voltage, resulting in a lager mount of power consumption. Although trimming can improve the precision, trimming itself will lead to further degradation of TC. Although some BGRs had been developed, most of them focused only on one aspect, i.e., to achieve a low temperature coefficient or a low power consumption or a high PSRR.

In this paper, to overcome the above mentioned problems, an alternative implementation which can achieve a high PSRR BGR with piecewise compensation is proposed. This paper is organized as follows. Section 2 presents the PSRR analysis of the conventional BGR in detail based on the corresponding PSRR small signal model. Section 3 introduces the design of the alternative high PSRR bandgap voltage reference circuit with piecewise compensation. Section 4 exhibits the simulation and measurement results in a 0.5 ​μm CMOS process. Conclusions are summarized in Section 5.

Section snippets

PSRR analysis of the conventional BGR

The principle of the BGR is to balance the negative TC of a pn junction with the positive TC of the thermal voltage.

The conventional BGR circuit is shown in Fig. 1. The output voltage VBGR and current IPTAT are given as:VBGR=VBE3+R2IPTATIPTAT=(VTlnn)/R1=(kTqlnn)/R1where, VBE3 is the base-emitter voltage of Q3, Ri is the resistance of Ri, k is the Boltzmann constant, q is the electric charger and T is the environment temperature. Equation (1) presents the dependence of VBGR on Vdd is only a

PSRR enhance mechanism

In this paper, an alternative implementation which can achieve a high PSRR BGR with piecewise compensation is proposed (schematically shown in Fig. 3.). Compared with the conventional circuit shown in Fig. 1, an extra branch is added to the PTAT structure and the diode-connected PMOS is performed at the additional branch. Hence the parallel of the inner resistances of M2 and M4 is accessed into the loop to increase the loop gain LGp which is defined as (4). Thus, its iPTAT is weaker correlated

Simulation and measurement results

The proposed BGR has been fabricated in 0.5 ​μm CMOS technology. The chip micrograph of the proposed BGR is shown in Fig. 5 and it’s active area is 170μm ​× ​140 ​μm. The device parameters of Fig. 3 are listed in Table I.

Fig. 6 shows the simulation result of TC between the conventional BGR circuit and the proposed BGR with the operating temperatures from −45 ​°C to 125 ​°C. Fig. 6(a) shows the maximum variation of the reference voltage is approximately 2 ​mV over a range from −40 ​°C to

Conclusion

A high PSRR BGR circuit with piecewise compensation has been proposed and implemented in a 0.5 ​μm CMOS technology. A high loop gain PTAT circuit and a PTAT2 circuit are both used to fine-tune the piecewise compensation so as to achieve high PSRR and low TC. The measured results illustrate the proposed BGR achieves the anticipated effects. The PSRR achieves 83 ​dB when the frequency is below 100 ​Hz, and more than 49 ​dB when the frequency exceeds 100 ​kHz. The TC reaches to 7.85 ​ppm/°C from

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