A tunable low noise high PSRR high accuracy bandgap reference using stacked-long cascode technique in 14 nm FinFET process
Introduction
Voltage references (VRs) are key circuits in electrical systems which require embedded block power supply. Usually VRs need a high precision reference voltage, and the bandgap reference (BGR) is a major way to provide it [[1], [2], [3]]. Precision bandgap voltage reference with low sensitivities to the process, the supply voltage and the temperature (PVT) have been widely used in mixed-signal integrated circuits (ICs) [[4], [5], [6]]. As the process node developed ahead, the embedded power supply is down. So the 1-V even sub-1V BGR is more necessary when the low power, low voltage and low-cost design in mixed-signal ICs [7,8]. To reduce power disturb [9], enhance the power supply rejection ratio (PSRR) of the electrical system, small process variation is very important. Process variation can decrease the performance of BGR due to current-mirror mismatch, resistor mismatch and tolerance, BJT or diode mismatch and offset of the operational amplifier (OP). (see Table 1, Table 2)
Process variations become more drastic along with IC process changed to metal gate device, the device distributed stress will affect the device quality. So the MOS FET with long channel lengths which needed in some mixed-signal IC for a current mirror or a larger output resistance (Rout) using have poor device matching [4]. MOS-like modeling transient analyses to avoid the channel lengths, the smaller output resistance, thus show satisfied device matching [10]. To achieve good mismatch, stack the MOS as long transistor to be a long channel MOS [11]. To compensate for process variations, trimming the resistors is normally used. Chopping technique is used in BGR to cancel the OPA offset, which needs OP area and chopping clock [6].
In this paper, a tunable BGR is presented where we use trimming technique to decrease the resistor variation, the chopping technique to decrease the offset of the OP amplifier which clamps the Vbe of the BJT. Especially the stack-long Cascode current mirror we also use dynamic element (DEM) to cancel the current mirror mismatch. The ripple which is introduced by chopping will be removed by a notch filter. The output of the BGR is tuned by the resistors.
The paper is arranged as follows. Section II error source and stack-long cascode are analyzed. Section III describes the error cancellation technique in the design. Measurement and conclusion are given in Section IV and Section V.
Section snippets
Error sources in CMOS bandgap reference
A conventional BGR structure is shown in Fig. 1. The bandgap voltage Vref is given bywhere VBE1 is the BJT’s base emitter voltage of Q1, , and the ΔVBE is the base emitter difference of Q1 and Q2, that gives the PTAT currentwhere N is the Q2 and Q1`s emitter area ratio.
Usually the non-ideal characteristics of this structure’s BGR are OP offset and device mismatch [1]. Device mismatch describes the differences in electrical behavior between
Resistance relative mismatch
For resistance, the mismatch (%) is calculated as the following expression:where is the relative factor mismatch of to . Suppose which value is about 0.1%–5% (eg. 1%) and R2 or R3 branch current is I2 or I3(I2=I3). We can get
Resistance absolute tolerance
When R1’ s absolute value change, it will change the PTAT current, then change the voltage of VBE. The R1will be changed to R1 ∗(1+), express the resistance absolute tolerance of R1. The VBE will change a small delta value,where is the thermal voltage, , then have (8), and is 5%.
BJT’s mismatch
The area ratio of Q1 and Q2 have error, which is marked with, and the offset voltage of the two devices isas , (16) can be expressed aswhere the can affect the PTAT current, the PTAT current changes, so the base-emitter voltage and the PTAT sub-factor will be affected, shown as (15), (16) and (17).
Early voltage factor mismatch
Early voltage can affect the PTAT current, so the VBE and IPTAT are all changed.where is the early voltage of the process.
As the change to , the VBE will change aswhere
The resistor temperature coefficient
We know that the resistor uses the same materials, so they have the same temperature coefficient. From this structure we have and , which can cancel the temperature coefficient.
Error cancellation technique
Now we change Figs. 1–3., replacing M1, M2 and M3 using the stack-long PMOS Cascode current mirror, and keep the mirror current as 1:1:1. Using dynamic element technique (DEM) switching the 3 paths PMOS structure. Using OP and chopping technique to cancel the offset of the two input nodes of the OP. Trimming the resistors of the structure. Add a notch filter circuit to cancel the ripple of the single output of the OP. The proposed circuit, Fig. 3 as follows.
The tunable resistor R4 is
Measurement results the simulated data
The BGR is fabricated in a 14 nm FinFET process. The chip photograph is shown in Fig. 8. And the die size is 40 μm∗90 μm, Fig. 9.
Fig. 10 show the large signal change affect with the chopping on, and then DEM on. We can achieve a good performance of the error cancellation technique. Fig. 11 shows the high PSRR results of the design, and Fig. 12 gives the power consumption, we can see a better power consumption. And last form Fig. 13 the low noise of different states is presented, no degraded
Conclusion
A tunable BGR design is proposed using the stack-long MOS cascade structure. Achieve a high precision BGR across the temperature range of −40 to 125. The die area is 0.0036 mm2, Power is 57μA and 3 inaccuracy is 1.2%, with high PSRR of 115 dB at DC and very low noise performance compare to the prior design. The error reduction techniques can be used in low-cost, low-power and advanced process nodes precision BGR design.
Declaration of competing interest
No conflicts of interest.
Acknowledgment
The authors also wish to thank Yuan Su and Qian Weng for their technique discussion and tape out supports. This work was supported in part by the National Major Project "2016ZX02301001-004 14 nm FinFET Basic IP Library" project.
Qiuliang Li received the B.S. degree from North University of China, Taiyuan, China, in 2006, and the M.S. degree from Fudan University, Shanghai, China, in 2015. Since 2016, he has been a Ph.D student at Fudan University, working on NB-IoT RX/analog front end and system design. His current research interests include designs of analog/RF ICs and mixed-signal ICs.
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Qiuliang Li received the B.S. degree from North University of China, Taiyuan, China, in 2006, and the M.S. degree from Fudan University, Shanghai, China, in 2015. Since 2016, he has been a Ph.D student at Fudan University, working on NB-IoT RX/analog front end and system design. His current research interests include designs of analog/RF ICs and mixed-signal ICs.
Lei Wu received the B.S. degree in Department of Electronic Science and Technology from Huazhong University of Science and Technology, China, in 2003, the M.S. degree in Microelectronics and Solid State Electronics from Huazhong University of Science and Technology, in 2007. Her research focuses on bandgap reference design and Process sensor, Voltage Sensor and Temperature Sensor development.
Ran Liu obtained his B.S. degree at Fudan University in 1982, M.S. degree at Shanghai Institute of Technical Physics of Chinese Academy of Sciences in 1985 and Doctor Degree in Natural Science at Max-Planck-Institute for Solid State Research and Stuttgart University in Germany in 1990. Dr. Liu’s research areas have included solid state physics, microelectronics, photonics, optoelectronics and bioelectronics. He has authored and co-authored over 400 peer-viewed journal articles and conference papers. He was an editorial board member for Journal of IET Circuits, Devices and Systems, Journal of Microelectronic Engineering and Journal of Frontiers Materials - Thin Films. He served as a technical program committee member for the International Conference on Micro and Nano Engineering (MNE) Conference and the European Solid-State Device Research Conference/ European Solid-State Circuits (ESSDERC/ESSCIRC) Conference.
LIU Yi received the MS and Ph.D. degrees from Tokyo University of Science in Japan, 1994 and 1997 respectively. He joined the faculty of the Tokyo University of Science, in 1997. Then he worked as a visiting professor at UCLA (University of California, Los Angeles) from 1999 to 2002. After that, he joined Microchip as a senior research fellow. Currently, he is a Professor and Ph.D. Supervisor at Nanjing University of Posts and Telecommunications. He has conducted many research projects funded by international companies and government. He has received Outstanding Contribution Awards of the Chinese-American professor. His research area is RF signal processing for the next wireless communications.