Associative processing using negative capacitance FDSOI transistor for pattern recognition
Introduction
In the Internet-of-Things era, smart devices, interconnected to each other, are expected to communicate and make appropriate decisions. This communication and decision making involves a lot of computations. Hence these devices must be able to do most of these computations by themselves, rather than relying on the cloud [1,2].
In the conventional computing systems, based on the von Neumann architecture, transistor scaling improves the computational capacity of the systems. However, with transistor channel length approaching the theoretical limit, alternative ways for improving the computational capacity of the systems are need of the hour [3]. Neuromorphic computing architecture, inspired by the human brain, is one such alternative. It performs parallel data processing and, hence, has the potential to provide significant improvement in computational efficiency, compared to conventional von Neumann architecture-based systems, for large-data computation applications.
In the neuromorphic computing domain, various designs of circuits, all having parallel architecture, are being explored [[4], [5], [6], [7], [8], [9], [10]]. Associative processing is a mechanism that is observed in the human brain, and used in neuromorphic computing systems for pattern recognition application.
Associative processing is a way of identifying a pattern by comparing the similarities between the input and the stored patterns [[10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21]]. The fundamental building blocks of the associative processing systems are the distance computing cells (DCC), whose outputs are a measure of the similarities between the input and the stored patterns. The digital CMOS-based implementation of the DCC requires large area and large energy-consuming circuits [10]. Hence, various novel circuits, exploiting the properties of emerging devices, are being investigated to implement the DCCs, to improve the performance of associative processing systems [11,13,21].
In this work, an area- and energy-efficient implementation of the DCC, which consists of only one negative capacitance FDSOI (NC-FDSOI) and four baseline FDSOI transistors, is presented. The NC-FDSOI transistor, used in the DCC has metal ferroelectric metal insulator semiconductor (MFMIS) structure, and is designed to give Gaussian-like current characteristics. An associative processing system is designed using the above NC-FDSOI based DCC. This system requires fewer transistors and, hence, consumes smaller area and lesser energy compared to conventional Boolean CMOS-based implementation. The functionality of the proposed NC-FDSOI based DCC is achieved in this small five transistor circuit because of the sharp switching of the ferroelectric polarization.
The output of the proposed NC-FDSOI based DCC is in binary voltage form, whereas the outputs of many other DCC implementations proposed that require small number of components, are in the form of analog current [[12], [13], [14]]. Moreover, some of the other proposed implementations also make use of emerging devices and are not yet matured [11,13].
The paper is organized as follows. In the next section, we present the associative processing system architecture used in this work. The qualitative comparison of conventional DCC characteristic and that of proposed DCC is provided in section 3. In section 4, we describe the transistors used in the circuit simulation, and in section 5, the design of NC-FDSOI transistor for getting Gaussian-like current characteristic is given. In section 6, the proposed DCC circuit is designed and analyzed. Section 7 contains the results and discussion of face recognition using the associative processing system. In section 8, the performance of the proposed system is compared with other known implementation techniques. The last section summarizes the conclusions drawn from the study.
Section snippets
Associative processing methodology
The associative processing system architecture used in this work is shown in Fig. 7(a). This architecture has m different pattern-score-computing-blocks (PSCBs) and can be designed to classify input patterns, into one of the m different classes. Input pattern, Vin, consisting of n voltage signals, Vin,1 to Vin,n, is applied in parallel to all the m PSCBs. Each PSCB i provides an output, that is a measure of the probability of input pattern to be that of class i. The outputs of all the m PSCBs
Proposed DCC characteristic and conventional DCC characteristic
In this section, the similarity between conventional DCC characteristic and that of the proposed NC-FDSOI based DCC is discussed. A block diagram representing operation of conventional DCC is shown in Fig. 2. A conventional DCC that operates on pixel i, receives two sets of voltages, Vin_i and Vcompare_i, and it computes as output the Euclidean distance () between the two sets of voltages. Therefore, the conventional DCC provides small output if the input voltage Vin_i
FDSOI and NC-FDSOI transistors
Fig. 3(a) and (b) show the measured current characteristics of the 50 nm technology node NMOS and PMOS baseline FDSOI transistors [22,23] used in this work. Simulations, in this work, are based on the characteristics of these two baseline transistors. The NMOS transistor is also used for designing the NC-FDSOI transistor in the DCC circuit.
Schematic of the MFMIS NC-FDSOI transistor used in the circuit is shown in Fig. 2. Voltage drop across the ferroelectric, Vfe, in NC-FDSOI transistor, is
Gaussian-like current characteristic using single NC-FDSOI transistor
As already mentioned in the introduction section, the DCC circuit proposed in this work consists of one NC-FDSOI transistor and four baseline FDSOI transistors. The NC-FDSOI transistor in the DCC is designed such that, for constant front gate voltage, VFG, the drain current, ID, increases with back-gate voltage, VBG, up to a certain point, after which the current decreases, giving us Gaussian-like current characteristic as shown in Fig. 4(a). The increase in ID with VBG is a known phenomenon
Distance computing cell
The proposed DCC circuit using the NC-FDSOI transistor, that gives Gaussian-like current characteristic, is shown in Fig. 7(a). In the figure, X2 denotes the NC-FDSOI transistor. The rest of the transistors used in DCC are baseline FDSOI transistors. Drain of the NC-FDSOI transistor is connected to load transistor, X1, transistor X3, and an inverter, as shown in Fig. 7(a). The output of inverter, Vout, is also the output of DCC circuit.
Here it is worth noting that all the transistors can be
Face recognition results
The performance of our associative processing system is validated by doing face recognition, using the database from Ref. [33] in this section. In this system, DCCs are controlled to operate only in two different states. From Fig. 11, we can see that the recognition accuracy of more than 90% can be achieved if all DCCs can be operated without any variations from their designed values. Fig. 11 shows the recognition accuracy that can be achieved, in case of deviation in VFG,N (front-gate voltage
Performance comparison
Comparison of the performance of the proposed system with the existing methods is shown in Table 1. The energy consumption of the proposed system, is obtained from SPICE and MATLAB simulations. For calculating the energy consumption in the associative processing system, 16-pixel images are used as input. Lower resolution images are used to simplify the energy calculations, and the numbers won't vary much with increase in image resolution, as the DCC circuit consumed most of the energy in the
Conclusion
An area- and energy-efficient associative processing system, using NC-FDSOI transistor based DCCs, has been presented in this work. Using the proposed system, the energy consumption per operation can be reduced by 2 orders of magnitude, compared to the conventional CMOS Boolean logic gate based system. With CMOS Boolean logic gate based implementation of one DCC requiring more than 100 transistors, the associative processing system with 1 NC-FDSOI and 4 FDSOI based DCCs is more area efficient
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Acknowledgments
Dinesh Rajasekharan thanks Sarvesh S. Chauhan, Amol D. Gaidhane and Chetan Kumar Dabhi for their valuable feedback. This work was partially supported by the Swarna Jayanti Fellowship (Grant No. – DST/SJF/ETA-02/2017-18) and FIST Scheme (Grant No. – SR/FST/ETII-072/2016) of the Department of Science and Technology, India.
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