A switched-capacitor power converter with unequal duty cycle for ripple reduction and efficiency improvement

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Abstract

This work applies unequal duty cycle to switched-capacitor (SC) dc-dc converters to improve its output ripple as well as the power conversion efficiency. By adjusting the duty cycle, the capacitor charge and discharge states are reasonably balanced. Therefore, we effectively reduce the output ripple and the charge redistribution loss, improving the efficiency. A SC converter verifies this scheme with voltage conversion ratios (VCRs) of 1/4 and 1/3, in a 65 ​nm CMOS low-power process. Operating with a switching frequency of 33 ​MHz, an input voltage of 2.4 ​V, an output range of 0.5–25 ​mA, and a VCR of 1/4, the peak efficiency increases by 1.0% and the output ripple drops by 43.6%, when compared with the equal duty cycle mode. With the input voltage equal to 1.8 ​V and the VCR ​= ​1/3, the peak efficiency increases by 0.7% and the output ripple reduces by 48.0%, compared to the equal duty cycle mode.

Introduction

Fully integrated switched-capacitor dc-dc converters are suitable for low-power Internet-of-Everything (IoE) applications, like wearable and medical devices. In such cases, SC converter has several advantages. Firstly, it has relatively higher power efficiency when comparing to linear regulators, while an SC converter with multiple voltage conversion ratios can achieve high efficiencies over a relatively wide input and/or output voltage ranges [1,2]. In addition, an SC converter can maintain high power efficiency under light load by modulating the switching frequency [3]. Secondly, SC converter shows fast transient load response with its first-order power stage [4,5]. Thirdly, capacitor has lower cost and smaller size, when compared to bulky power inductor in a switching mode power converter. Moreover, SC converter may generate less electromagnetic interference (EMI) to the system [6].

To obtain a clean supply, a linear regulator is usually used in cascade with a switching converter [7], but it reduces the power delivery efficiency. If we can reduce the output ripple of a switching converter, the power supply rejection requirement on the linear regulator stage can be relaxed, or potentially eliminating the post-stage linear regulator and thus increasing the system efficiency.

Fig. 1 shows the circuit techniques that can be used to reduce the output ripple of an SC converter. For on-chip implementations, the multiphase interleaving scheme (Fig. 1(a)) can be easily used to reduce the output ripple with negligible power and area overhead [5]. Alternatively, digital capacitance modulation (Fig. 1(b)), which divides the total flying capacitor into binary-weighted parts that modulate the output voltage and reduces the output ripple [8]. However, for an SC converter with off-chip capacitors, we do not have the luxury to employ interleaving phases with a large number of flying capacitors, which significantly increase the cost and complexity [9]. In such case, switch on-resistance modulation (Fig. 1(c)) and pulse-width modulation (Fig. 1(d)) were introduced to reduce the output ripple. For the switch on-resistance modulation in Ref. [8], dividing the switches into multiple parts equally and controlling them according to the load current can effectively reduce the output ripple. In Ref. [6], a structure with a three-stage switchable amplifier driving the power switch is proposed to modulate the on-resistance through changing the gate-drive voltage of the switch. For pulse-width modulation, the output ripple is usually reduced by partially charging the capacitor [10]. However, the partial charging method does not make full use of the capacitors, as the amount of charge delivered per phase is not equal. In this case, limiting the charging and discharging duration will affect the output voltage and power conversion efficiency. To solve the unbalanced charge delivery problem, multiphase balanced switching scheme was proposed, which reduces the output ripple by distributing the total charge evenly across each conversion phase and by replicating one or more conversion phases in one full conversion cycle [11]. This scheme can also be applied to dual-output SC dc-dc converters for reducing the cross regulation among the two outputs [12]. In short, simple but effective control schemes are favorable.

In this paper, we introduce a new method that uses the unequal duty cycle to reduce the output ripple, and also to increase the power conversion efficiency. Section 2 introduces the working principle of the unequal duty cycle scheme, presents the circuit implementation of the SC converter, discusses, and compares the proposed scheme with the multiphase balanced switching. Section 3 gives the simulation results. Finally, Section 4 draws the conclusions.

Section snippets

Principle of the unequal duty cycle

The basic idea of the unequal duty cycle scheme is to deliver the charge evenly from the converter to the load among each phases. Then, the energy transfer process goes more smoothly, and therefore, reducing the output ripple. At the same time, the charge redistribution loss can also be reduced in the duty cycle adjusting process, obtaining a higher output voltage and improving the power conversion efficiency. The charge redistribution loss can be expressed by:Ploss_redistributionCΔV2fswwhere Δ

Ripple improvement

Fig. 6 and Fig. 7 show the output voltage and output current waveforms of the transistor-level simulations in a standard 65 ​nm low-power CMOS process. The total flying capacitor is 3.2 ​nF, and the load capacitor CL is 1 ​nF. By assuming the on-chip capacitor density to be 15 ​nF/mm2 [13], and assuming the sizes of switches and controller are small when comparing to the capacitors, the estimated chip area of this design is within 0.3 ​mm2.

Within each operation phase, we can define two states.

Conclusions

In this paper, we proposed a fully-integrated switched-capacitor dc-dc converter with an unequal duty cycle scheme. Compared to the equal duty cycle, the unequal duty cycle scheme reduced the output ripple, and more efficiently completed the charge distribution, leading to an increase of the output voltage and the power conversion efficiency.

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Acknowledgments

Work funded by the Research Committee of University of Macau (under MYRG2017-00037-AMSV), and the FDCT-NSFC joint project 006/2016/AFJ, and the International Science & Technology Cooperation Program of Guangzhou (201807010065).

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    However, they need a large area which limits the power density of a PMIC [4]. On the other hand, switched capacitor DC-DC converters are offering a small area and superior power density but with moderate efficiency [5–7]. Hybrid solutions hence offer an attractive means to potentially increase power density and/or efficiency [8–10].

1

On leave from IST.

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