A sub-1V dual-path noise and distortion canceling CMOS LNA for low power wireless applications

Abstract

This paper presents a 0.8 ​V supply voltage low noise amplifier (LNA) with high linearity for low power wireless applications. To reduce both second- and third-order intermodulation components (IM2 and IM3), the proposed structure creates equal common-mode (CM) currents with the opposite sign by cascading two differential pairs with a cross-connected output and improves linearity. Using resistive feedback together with noise and distortion canceling technique mutually cancel noise and nonlinearity of both main and auxiliary amplifiers. Combining transformer-based gm-boosting and current reuse techniques makes the presented LNA a superior candidate for low power radios. Detailed analysis and simulations are provided to show the effectiveness of the proposed LNA structure. Simulation results using 65 ​nm CMOS process reveal that the linearized low power LNA achieves over 25 ​dB voltage gain, 2.7 ​dB NF, +10.1 dBm IIP3, and average IIP2 of more than +57 dBm while consuming 870 ​μW.

Introduction

Nowadays, reducing the cost, form factor, and power consumption while keeping the performance are highly demanded in radio frequency (RF) transceivers especially for wireless communications such as Bluetooth low energy (BLE), internet of things (IoT), wireless sensor network (WSN), and 5G. These aims are achieved by moving toward system-on-chip (SoC) designs, which integrate more and more components and eliminate off-chip devices such as surface acoustic wave (SAW) filters and duplexers [[1], [2], [3], [4], [5]].

LNA is a power-hungry block in an RF front-end. Therefore, designing the high linearity low voltage low power LNA in SAW-less radios is deeply challenging because of their stringent specification requirements such as the linearity, which is due to the huge number of un-filtered interferers. Various methods are reported to improve the linearity in LNAs [6], which are mainly focused on only IIP3 enhancement rather than IIP2, thanks to the pre-filtering especially in narrow bandwidth applications. However, in SAW-less and broadband receivers both second and third inter-modulations have to be alleviated because both close and far blockers are received by the LNA, creating high second and third order intermodulation, respectively and degrading the sensitivity of the receiver [4]. Among different LNA linearization methods like derivative superposition (DS) [7,8], IM2 injection [9], noise and distortion cancellation [[10], [11], [12]], and post distortion [13], DS method is more helpful for both IM2 and IM3 reduction [10,11]. Caprio’s cross-quad and Quinn’s cascomp techniques are also widely used in differential linearized circuits [[14], [15], [16]] but they suffer from the instability and NF degradation. In Ref. [17], a broadband LNA has been presented that improves the linearity by utilizing the feedforward technique while degrades the NF. The presented LNA in Ref. [18] improves both the linearity and noise figure by adding two extra transistors to the feedforward technique proposed in Ref. [17], and cancels both distortion and noise of the input transistor in the common gate (CG) structure at the same time; however, it consumes 14 ​mW.

Besides, different methods have been reported to reduce the LNA power dissipation in order to meet the power requirement in low power applications such as BLE and short links that has tight power budget [[19], [20], [21], [22]]. Lowering the supply voltage is one of them, that saves power in SoC radios, which includes digital blocks ($p_{dc}\approx C{V}_{dd}^{2}f$). However, as a drawback, this method suffers from the non-linearity of g_ds due to the limited voltage headroom. Therefore, in ultra-low supply voltage LNAs, the use of big inductive loads that occupy large die area is inevitable [21,22]. Reusing the current of circuit branches is another way for power saving at the expense of the linearity and bandwidth reduction. It also poses the isolation problem especially when is used between different blocks with different functions in a receiver chain. For instance, in Ref. [23], the stacked RF front-end reduces the power consumption to 600 ​μW by reusing the current, but suffers from low linearity (IIP3 ​= ​−16.8 dBm) and high NF of 15.8 ​dB. Since the input g_m of CG LAN is limited to 20 ​mA/V, g_m boosting is also an effective technique to reduce the power consumption in wideband applications especially for BLE and WSN, which require relaxed specifications [22,24].

In this paper, a CG LNA suitable for low power applications like BLE has been presented in which the common mode canceling structure is combined with the feedforward path and resistive feedback loop, in order to improve both the linearity and NF. To lower the power consumption, the transformer-based passive g_m-boosting and current reuse techniques are also utilized. To improve the linearity, the output intermodulation current of input CG devices has been canceled by adding two auxiliary pairs that create equal and out-of-phase IM components. Noise of CG and auxiliary pairs are removed via a feedforward noise canceling structure and a resistive feedback path, respectively. Passive g_m-boosting using transformer increases the source resistance at the input of the CG LNA and provides low power input matching.

In section 2, the proposed LNA and the mechanisms of noise, linearity and power improvement are described. In addition, a brief explanation over the transformer model, design consideration and their effects on the LNA performance is presented. Section 3 provides a detailed analysis on the stability, input matching, gain, noise figure, and linearity. The simulation results are presented in section 4. Finally, section 5 concludes the paper.