Improved modeling of flicker noise including velocity saturation effect in FinFETs and experimental validation
Introduction
The modeling of low frequency noise (or flicker noise) is very crucial for low power analog circuit design. The flicker noise models need to capture the noise characteristics over different operating regions of scaled devices, for accurately predicting the performance of low noise analog and high speed digital integrated circuits. With the capability of up conversion of frequency, the effect of low frequency noise can be seen in high frequency circuits [1,2]. Hence, extensive research has been performed to study low frequency noise (LFN) [[3], [4], [5], [6]]. There are two leading theories to explain LFN in Si devices: (1) carrier number fluctuation (△N) due to trapping/de-trapping and (2) mobility fluctuation (△μ) [7,8]. Several models have been suggested in the literature to model LFN [[9], [10], [11], [12], [13], [14], [15], [16], [17]], but the unified flicker noise model is widely accepted model for circuit simulation [10,11]. The unified flicker noise model has been used in all BSIM models (BSIM4, BSIM-BULK, BSIM-CMG, BSIM-IMG) since the early days due to the simplicity of its implementation in the circuit simulator. However, [10,11] have not considered the impact of velocity saturation (VS) in their formulation. Arnaud et al. [12] have developed a unified model for 1/f noise, which is valid for different gate bias regimes i.e., weak inversion, strong inversion, and even moderate inversion, but the effect of VS has not been incorporated in this model. Authors in Refs. [14,15] have demonstrated the analysis and modeling of 1/f noise variation in non uniformly doped devices. Ref. [16] shows the improved analytical model of 1/f noise that uses unified 1/f noise approach for the halo implanted MOSFETs and it is implemented in the charge-based BSIM-BULK model, but it also does not discuss the impact of VS effect in 1/f noise. Ref. [17] explains the effect of traps distribution in state-of-the-art FINFETs on 1/f noise and presents an improved model of 1/f noise model in the weak inversion region. However, it uses unified flicker noise model of BSIM-CMG for the strong inversion region. Ref. [13] explains the effect of VS in the improved model of 1/f noise. Since the improved model of [13] is not established on the unified noise expression, it can not be directly implemented in the BSIM models in its present form. In this work, we incorporate the effect of VS in the unified expression of PSD and verify it (under the framework of BSIM-CMG) with measured data. Our improved 1/f model can also be easily implemented in any other BSIM models.
In this work, we compare Berkeley Short Channel IGFET Model - Common Multi Gate (BSIM-CMG) [18] with measured data of 14 nm node FinFET. In Fig. 1, drain noise power spectral density (SID) versus frequency is shown for different bias conditions for the PMOS device. In addition to △N and △μ, velocity saturation (VS) also has significant impact on LFN [19] in short channel devices through mobility degradation [20] and it is not modeled in flicker noise model of BSIM-CMG. Hence in Fig. 1, we can see that BSIM-CMG accurately predicts the noise power in the linear region, but, in the saturation region, it overestimates the SID.
BSIM models are so matured that they have the excellent fitting of dc characteristics with experimental data. Once the dc parameters are extracted, BSIM-CMG unified model has NOIA, NOIB, and NOIC parameters to capture the dependency of LFN over different bias conditions. However, the accurate fitting of drain current noise power spectral density is not obtained by tuning of these existing parameters as seen in Fig. 1. Hence in this work, the BSIM-CMG unified noise model is reexamined and a new model is proposed to capture the noise behavior for different bias conditions, for advanced technology nodes.
The paper is organized as follows: In Section II, the limitation of the existing noise model is highlighted and possible cause of abnormal behavior of low frequency noise model is described. Section III presents the methodology used to develop the proposed model. Section IV explains the results and shows the validation of the proposed model. Conclusions are drawn in section V.
Section snippets
Limitations of BSIM-CMG noise model
We start our discussion with the existing implementation of low frequency noise model in BSIM-CMG given by (1). It is expected from (1) that, in the linear region of operation, △Lclm should be zero and the drain side charge should be calculated from Vds. In the saturation region of operation, the model uses the approximation that channel is divided into triode and pinch off region [21]; 1st part of (1) is for triode region (charge densities at left and right ends of triode region are different)
Compact modeling of flicker noise
It is well known that noise modeling is two-step calculation: first, to calculate local noise source and second, to calculate how noise propagates from channel to output terminal [20]. In the saturation region of operation, the channel is not uniform throughout the length and, hence, local noise source and noise transfer function change along the length of the device. To address this issue, we begin as [11].where q is electron charge, k Boltzmann constant, T
Results and discussion
The basic approach to develop low frequency noise model in this work is based on the methodology of [22,25]. The accuracy of 1/f model depends on the dc model that can precisely predict the dependence of drain current for different bias conditions. In Fig. 3(a–d), DC model calibration is performed by plotting IDS − VGS, gm − VGS for VDS = −0.05V, −0.75V, −1.5V and IDS − VDS for VGS = −0.3V to −1.7V. We have used global parameter extraction so that a single set of parameters fit all channel
Conclusion
An improved model of flicker noise, including velocity saturation effects in the industry standard BSIM-CMG framework, is presented in this work. The proposed model is generic and, hence, it can be implemented with slight modification in the existing industry standard noise models, such as BSIM-BULK, BSIM-IMG etc. Limitations of the state-of-the-art noise model are also highlighted. The improved model accurately captures the experimental data for different bias conditions from an advanced
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Acknowledgments
The authors thank Sarvesh S. Chauhan for his valuable feedback. This work was partially supported by the Swarnajayanti Fellowship (Grant No. – DST/SJF/ETA-02/2017-18) and FIST Scheme (Grant No. – SR/FST/ETII-072/2016) of the Department of Science and Technology, India and Berkeley Device Modeling Center (BDMC).
References (25)
- et al.
Low frequency noise in mos transistors—i theory
Solid State Electron.
(1968) 1/f noise
Phys. B+C
(1976)- et al.
Low-frequency noise investigation and noise variability analysis in high-k metal gate 32-nm cmos transistors
IEEE Trans. Electron. Dev.
(2011) - et al.
The impact of device type and sizing on phase noise mechanisms
IEEE J. Solid State Circ.
(2003) - et al.
1/f noise in mos devices, mobility or number fluctuations?
IEEE Trans. Electron. Dev.
(1994) - et al.
Low-frequency fluctuations in solids: <inline>\frac{1}{f}$ noise
Rev. Mod. Phys.
(1981) - et al.
Flicker noise performance on thick and thin oxide finfets
IEEE Trans. Electron. Dev.
(2017) Characterization of low 1/f noise in mos transistors
IEEE Trans. Electron. Dev.
(1971)- et al.
Noise modeling for rf cmos circuit simulation
IEEE Trans. Electron. Dev.
(2003) - et al.
A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors
IEEE Trans. Electron. Dev.
(1990)
A physics-based mosfet noise model for circuit simulators
IEEE Trans. Electron. Dev.
A compact model for flicker noise in mos transistors for analog circuit design
IEEE Trans. Electron. Dev.
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