A digital background calibration scheme for non-linearity of SAR ADC using back-propagation algorithm

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Abstract

A new digital background calibration scheme for non-linearity of successive approximation register (SAR) analog-to-digital convertor (ADC) is presented. Since non-linearity of high resolution SAR ADC is mainly caused by the difference between the real and ideal weights of capacitor digital-to-analog convertor (CDAC) with respect to the normalized-full-scale, calibration of weights of more significant bits is necessary when the resolution of SAR ADC comes to more than 12 bits. By using back-propagation algorithm to train the normalized real weight of more significant bits (MSBs) in neural network without any change in SAR ADC circuit design, the calibration table for each bit is implemented and updated in the digital domain without interrupting normal ADC process, which is used to correct the raw SAR code in the background to improve the performance of ADC, which is suitable for some detection applications in particular circumstances. In MATLAB simulation, the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of a 14-bit with 1-bit redundancy SAR ADC model are improved to 85.59 ​dB and 97.27 ​dB from 56.65 ​dB to 77.07 ​dB using the proposed calibration scheme, at a standard deviation of a unit capacitor of 2%.

Introduction

Charge redistribution SAR ADC has been a popular solution for medium-to-high resolution applications due to the advantage of simple structure and energy efficiency [1,11]. When the resolution of successive approximation register (SAR) analog-to-digital convertor (ADC) comes to more than 12 bits, the deviation of unit capacitor and the parasitic capacitance in fabrication process greatly deteriorate the linearity of SAR ADCs [6]. Since non-linearity of SAR ADC is mainly caused by the difference between the real and ideal weights of capacitor digital-to-analog convertor (CDAC) with respect to the normalized-full-scale, linearity calibration is necessary [3].

Many linearity calibration schemes have been proposed to deal with the capacitor mismatch, which can be categorized as analog-domain calibration and the digital-domain calibration. Analog-domain calibration schemes like [4] detect and compensate the analog capacitors to the idea weights directly in conversion process, which limits the speed of bit trial in conversion process and need additional compensation capacitors and complicated logic control circuits [10]. uses Metal-Oxide-Semiconductor transistors capacitors (MOSCAPs) as CDAC and exploit the body terminal of these MOSCAPs to adjust their capacitance and correct process mismatches. However, this design is prone to process, voltage and temperature (PVT) variations because of analog control signals, which limits its applications.

With development of the Complementary Metal-Oxide-Semiconductor (CMOS) technology, digital-domain calibration schemes become popular due to reduction of dire area and power consumption in digital domain. In Refs. [3,5,6], similar calibration methods are represented, which use the capacitors of less significant bits (LSBs) to quantize weights of more significant bits (MSBs) without extra analog circuit. They find the real weights of MSBs in calibration mode and correct the raw output in the digital domain in conversion mode. However, these schemes are foreground calibration and need an extra long-time calibration phase [7]. infers the capacitor weights of a SAR ADC with the help of a channel-shared high resolution sigma-delta ADC, which obviously unpractical due to great increase in design complexity and die area.

An architecture for digital background calibration of SAR ADC called ‘split-ADC’ are also represented in Ref. [8], which split a single SAR ADC into two independent same ADCs converting the same input and corrects SAR ADCs' linearity errors through least-mean-square (LMS) algorithm in the background. However, the capacitor mismatches are complicated to extract because of other non-ideal factors of sampling timing, offset, and gain mismatch in two ADCs' analog circuit. A perturbation based digital calibration method is reported in Ref. [2], in which two opposite perturbation signal are add to input to extract the mismatch error and LMS iteration algorithm is also utilized in the background to correct bit error. It has the same problem as [9] due to two ADCs' architecture.

In this paper, we propose a data-dependant linearity calibration scheme using neural network to train the weight of MSBs in the background so that the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of SAR ADC are greatly improved. Compared with other technologies of calibration, the proposed scheme can correct the capacitor mismatch without the need of any changes in SAR ADC design and the calibration algorithm runs in the background without interrupting the foreground normal ADC operation. This full digital background calibration scheme is suitable for some detection applications in particular circumstances which need real-time calibration and can be efficiently implemented on System on a Chip (SoC) to facilitate a high resolution SAR ADC because of these features. This paper is organized as follow: In section 2, we provide a brief overview of previous work on digital background calibration schemes for SAR ADC. The architecture of proposed scheme and the calibration structure using neural network are presented in Section 3. The simulation results are shown in Section 4. Finally, Section 5 concludes this paper.

Section snippets

Typical digital-domain linearity calibration

A conventional charge redistribution 14-bit SAR ADCs analog model is shown in Fig. 1 [3,6]. Normal SAR ADC operation starts from sampling and holding. During sampling phase, the differential input signal VIN,P and VIN,N are sampled on the bottom plate of CDAC, while common-mode voltage VCM is connected to both side of the top plates. After sampling, the switches of VIN,P, VIN,N are disconnected in holding phase and charge transfers to the top plates of CDAC which are connected to the

The proposed digital-domain background calibration scheme

From the brief of conventional digital calibration in the previous section, we can demonstrate that the non-linearity of high resolution SAR ADC can be corrected by using real weights of MSB segment and raw digital output of ADC to calculate the calibrated results in digital domain.

To test the linearity of SAR ADC during ADC operating, total harmonic distortion (THD) is presented as an essential measurement for the linearity of SAR ADC in the analysis of dynamic performance of ADC. It is the

Simulation results

To verify the linearity calibration of the proposed scheme, a behavioral model of a 14-bit charge redistribution SAR ADC based on CDAC architecture is designed as shown in Fig. 1, which includes KT/C noise and comparator's noise met the command of 14-bit resolution, as well as the standard deviation of a unit capacitor at 2% and the effect of parasitic capacitances of LSBs segment and bridge capacitor at 1%. And input signal is close to full-wave swing.

Table 1 show an example of simulated

Conclusion

This paper presents a data-dependent calibration scheme for non-linearity of SAR ADC. The proposed calibration scheme can calibrate capacitor mismatch of SAR ADC in the background without interrupting normal SAR ADC process. A back-propagation algorithm is proposed to train the normalized weight errors of SAR ADC in the digital domain, which settles the issues of complexity computation. Moreover this scheme needs no change in circuit design, which can be efficiently implemented on SoC to

Author statement

Hao-wei Lu: Conceptualization, Methodology, Writing- Original draft preparation. Xiao-peng Yu: Visualization, Investigation. Si-Qi Wang: Validation. Yu-Yan Liu: Writing- Reviewing and Editing. Zhen-Yan Huang: Validation. Zheng-hao Lu: Supervision. Kiat-Seng Yeo: Writing- Reviewing and Editing; Jer-Ming Chen: Writing- Reviewing and Editing.

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Acknowledgement

This work was supported by NSFC-Zhejiang Joint Fund for the Integration of Industrialization and Information under grant number U1709221 and National Natural Science Foundation of China under grant number 61574125.

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