Equal-slope baud-rate CDR algorithm with optimized eye opening

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Abstract

A novel equal-slope baud rate clock and data recovery (CDR) algorithm is proposed. By positioning the locked point on pulse response where pre-cursor slope and main-cursor slope are equal, an optimized eye-opening is achieved with enhanced eye height, eye width and timing margin. The algorithm is realized in high-speed wireline receiver by finding the sampling position with maximum probability over an adaptive reference voltage when adjacent two data are opposite, with a double transition density over conventional Mueller-Muller (MM) algorithm. With no need for extra power-consuming or timing-critical circuits, this algorithm is readily integrated into prevalent decision feedback equalization (DFE). Simulation shows more than 18.0%, 14.4% and 56.1% improvement in recovered eye height, eye width and time margin, respectively, over its MM counterpart with >10 ​dB channel loss@14 ​GHz. Clear eye improvement could also be seen with respect to classical bang-bang CDR. Moreover, equal-slope CDR demonstrates significant locked point stability against system noise thanks to alienation from nearly-flat region.

Introduction

In recent years, applications such as Internet of Things and Artificial Intelligence have been the main driving force behind a constant-growing serial-link speed. On receiver side, while ADC-based scheme has demonstrated its capability of compensating high loss in long reach (LR) applications [[1], [2], [3]], its mixed-signal counterpart finds position in short reach (SR) and medium reach (MR) scenario with better power efficiency [[4], [5], [6]]. However, an ever-increasing data rate poses two challenges to the mixed-signal receiver design. On one hand, system power budget becomes even tighter as more high-bandwidth schemes start to be utilized at the cost of prohibitive power, potentially counteracting scheme's inherent benefits. On the other hand, a more accurate equalization is required due to deteriorating channel characteristics in frequency over ~10 ​GHz to meet certain bit error rate (BER) standard. In response to the former, baud-rate clock and data recovery (CDR) has been favored over 2x oversampling method with advantage in power saving by halving samplers and clock frequency [[7], [8], [9]]. Though widely used, conventional Mueller-Muller (MM) algorithm [2,3,7] fails to make the maximum of equalization hardware cost by producing a suboptimal sampling point.

By virtue of the shared data and error information from decision feedback equalizer (DFE) normally used in high-speed receiver, MM-CDR finds its locked point τ on pulse response of the link h(t)(typically including channel, continuous-time linear equalizer (CTLE), variable gain amplifier (VGA) and DFE), where pre-cursor h(τT) and post-cursor h(τ+T) are equal, and T denotes one unit interval(UI) of data, as can be seen in Fig. 1a (4-tap DFE is used in the example). With h(τ+T) cancelled out by DFE, h(τT) is forced to be around zero. But having an asymmetrical pulse response in most cases, MM-CDR will lock to an underperformed position [10], which can be indicated from its recovered eye. Apart from that, as the slope near h(τT) is rather slow, MM algorithm's susceptibility to noise grows, leading to a recovered clock with degraded jitter performance.

Research on the methods of finding an optimized sampling position has been conducted over the years. As the ultimate goal of optimization, BER offers the highest accuracy on deciding an optimal sampling point. Given the timing penalty of BER measurement, [11], introduces a substitutional pseudo-BER as criterion, yet it still suffers from long convergence process under less-than-low target-BER situation (e.g. 10−4), even with the help of external computer. Recovered eye diagram, on the other hand, provides effective information about clock recovery without the necessity to count errors through tons of data, which gives rise to approaches based on eye-opening monitor (EOM) [12,13]. By defining parameters such as code mismatch error rate (CMER) [12] or decision threshold based on sigma-tracking [13], one could acquire an eligible result of eye-opening size, and hence an optimal sampling phase. Nevertheless, the alleviated time-consuming issue still remains thanks to their iterative nature, leading to schemes more straightforward on timing recovery [14,15]. [14] presents a design which shifts the sampling point towards the DFE-unequalized position by adding a digital offset to the phase-error accumulator, however its target position is not performance-oriented and manual adjustment is needed when applying prevalent binary phase detector. [15] proposes a CDR with maximum-eye-tracking ability, but requiring two sampling phases each UI with timing difference ΔT apart for phase detection, whose sensitivity to PVT might result in a reduction of sampling accuracy, unless extra care is taken for delay control.

In this paper, rather than implementing error counting or EOM, theoretical recovered eye-diagram is first analyzed for typical mixed-signal receiver. Accordingly, the proposed equal-slope algorithm finds its sampling target with an optimized eye-opening, where the slope of pre-cursor and main-cursor are equal, i.e. h(τT)=h(τ), on the pulse response, as shown in Fig. 1b. Running at baud-rate, the algorithm adds no additional hardware cost to that of MM, while shows tremendous improvement in recovered eye margin.

Rest of the paper is organized as follows. Initially, Section II provides the theoretical foundation for the optimization equal-slope algorithm brings along. Thereafter, a generic receiver architecture realizing the algorithm is presented in Section III whereas its simulation results are shown in Section IV. The conclusion is drawn in Section V.

Section snippets

Principle analysis

With presence of system noise and jitter, the definition of optimal sampling point should correlate to quality recovered eye opening both vertically and horizontally, achieving optimized BER in a specific equalization scheme. As shown in Fig. 2, fully-closed received eye (Fig. 2a) reopens with the help of proper equalization setting (Fig. 2b). The drastic change on UI border comes from an adoption of DFE [16]. Illustrated in Fig. 2b, the recovered eye height EH corresponds to the minimum

Circuit implementation

A generic high-speed receiver architecture embedding the proposed equal-slope baud-rate CDR is shown in Fig. 5. The input data runs at a typical speed of 28 ​Gb/s, coming into an analog front-end made up of CTLE and VGA whereas phase locked loop (PLL) and poly phase filter (PPF) generate the quarter rate clock needed. Just like MM implementation, the CDR loop comes closely with DFE, sharing the required data and error information for phase detector.

Principle of phase detection is explained as

Simulation results

Equal-slope and MM baud-rate CDR are simulated in the generic receiver architecture under a variety of channels with incremental loss. Commonly-used bang-bang (BB) CDR also gets involved into the comparison. For a time-efficient evaluation of the proposed algorithm, system-level simulations have been done in MATLAB, with key parameters such as CTLE and VGA frequency response, DFE critical path delay as well as typical channel S-parameter captured in 28 ​nm CMOS process to characterize the real

Conclusion

The proposed baud-rate CDR algorithm excels in recovered eye opening by finding the equal-slope position for main-cursor and pre-cursor on pulse response, which helps optimized the utility of power-consuming DFE equalization. For a typical high-speed receiver scheme consisting of CTLE, VGA and DFE, the presented equal-slope algorithm improves eye height, eye width as well as timing margin over conventional MM and bang-bang algorithm. Simulation shows its effectiveness in recovered eye

Author contribution

Xiao Xiang:Conceptualization, Methodology, Software, Writing-Original Draft, Weixin Gai: Supervision, Writing-Reviewing and Editing, Ai He: Data curation, Hang Zhou: Resources, Yanchi Dong: Visualization

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Acknowledgments

This work was supported by the National Key R&D Program of China (Grant No.2018YFB2202301).

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