Digital lock in amplifier: study, design and development with a digital signal processor

doi:10.1016/j.micpro.2003.12.002

Microprocessors and Microsystems

Volume 28, Issue 4, 20 May 2004, Pages 157-162

https://doi.org/10.1016/j.micpro.2003.12.002 Get rights and content

Abstract

In this work, the study, design and development of a Digital Lock In Amplifier (DLIA) with a Digital Signal Processor (DSP) DSP32C from AT&T is presented. To synchronize the DLIA oscillator with external signal, a Discrete Phase Locked Loop (DPLL) is added to the systems. A theoretical introduction of both systems is also presented. The algorithm of the DPLL presented is valid only for constant uniform sampling frequency.

Introduction

The Lock In Amplifier (LIA) is a useful instrument in Research and Development Laboratories. It is used to measure small sinusoidal signals, even when these signals are masked by noise. The excitation of the system under test can be generated either internally or externally. In case of external excitation, it is necessary to synchronize the LIA oscillator with the incoming signal, so a Phase Locked Loop is required. In this work, we present an algorithm that allows us to handle the Digital Lock In Amplifier (DLIA) and the Discrete Phase Locked Loop (DPLL) by means of Digital Signal Processor (DSP) assisted by a microprocessor. This configuration allows us to work in real time. The advantage of the digital systems instead of the analog ones is its accuracy. The digital system avoids harmonic distortion and thermal shifting arising in the analog multiplier, as well as the versatility for fitting functional parameters [1]. This work presents an approach to design both DLIA and DPLL and its implementation with a DSP. The distinct idea of the proposed system is the inclusion of the DPLL to track the LIA oscillator with external source signal.

Section snippets

Basic lock in amplifier theory

Fig. 1 shows the basic Lock In Amplifier (LIA) configuration (internal source). It is composed by the oscillator, two multiplier stages and two low pass filters.

For simplicity, quantization noise introduced by both ADC and DAC is not considered in the analysis. The reference signal generated by the LIA oscillator has the components $v_ref_sin_{n} = sin (Ω_{ref} n)$ $v_ref_cos_{n} = cos (Ω_{ref} n)$ where $Ω_{ref}$ is the discrete reference frequency.

The system response signal is expressed as $v_sig_{n} =V_{sig} sin (Ω_{sig} n+θ_{sig})+η_{n}$ where V

Lock in filter

Fig. 2 shows the filter used in the LIA. It is a simple zero-pole low pass filter.

The transfer function of this filter is: $H(z)= Y(z) X(z) = (1−a)z z−a$ The value of the coefficient filter, a, is obtained as $a= exp −2 π Freq_{cut} Freq_{sample}$ where Freq_cut is the filter cut off frequency, Freq_sample is the sampling frequency.

This expression shows that the LIA bandwidth detection depends on the filter cut off frequency, which can be set by the user. If the system under test is excited by an external source, the

Basic discrete phase locked loop theory

Fig. 3 shows the basic Phase Locked Loop configuration. It is composed by the phase detector which, in this case, is an adder plus a multiplier stage, a loop filter and finally a Digitally Controlled Oscillator (DCO).

The phase detector error signal, e_n, is obtained as: $e′_{n} = 12 [sin (θ_{n} −ϕ_{n})+ sin (2Ω_{0} n+θ_{n} +ϕ_{n})− sin (2Ω_{0} n+2ϕ_{n})]+η′_{n} cos (Ω_{0} n+ϕ_{n})$ The sinusoid-noise product can be replaced by a new random variable η_n. If θ_n≈ϕ_n, the previous expression can be approximated by: $e′_{n} ≅ 12 (θ_{n} −ϕ_{n})+η_{n}$ The factor 1/2 can be

Digital controlled oscillator

The Digitally Controlled Oscillator (DCO) is the most critic part of the development because the whole instrument performance depends on this stage. The requirements for the DCO are the following.

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Reduced processing time.
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Dynamic frequency synthesis.
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Synthesis of two quadrature signal.
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Low harmonic distortion.

One way to accomplish these requirements was the use of the sine lookup table oscillator combined with a linear interpolator [4]. Fig. 7 shows the DCO stages for sine function synthesis. For

Estimated amplitude loop

It can be seen that if the input reference amplitude is not equal to the DCO estimated signal amplitude, the DPLL response oscillates near the desired locked phase. To avoid this problem, an amplitude loop estimator is added to the system as it is shown in Fig. 9 (upper section). In this figure we also include the phase estimator (lower section) completing the DPLL system.

By including the amplitude estimator in the system, we avoid the problem described above and improve the DPLL performance.

DPLL coefficient

The values of the DPLL coefficient k₁ and k₂ are determined by Eqs. , . These expressions are very complex to calculate in the DSP, with a lot of time consumed, so a polynomial approximation is used instead. The DPLL settling time is a function of the value k_a. To derive it, we begin with the following transfer function and the equivalent discrete time response signal: $G(z)= ϕ(z) θ(z) = z^{−1} k_{a} 1−(1−z^{−1})k_{a} y_{n} =1−(1−k_{a})^{n}$ To obtain k_a we look for a value that satisfies the identity: $y_{n} =1−(1−k_{a})^{n} =1− 1 e$ That is: $k$

Frequency and amplitude estimation

To avoid the DPLL dead time waiting to lock an input signal, it is desirable to speed up the process. This can be accomplished by setting the value ω_free close to the frequency of the input signal. To do that, an amplitude and frequency estimator is used. The algorithm is based on counting the zero crossing points in a fixed interval of time. Then an estimate of the normalized frequency is calculated as $f_{n} = N_{Zerocrossing} 2N_{Count}$ where f_n is the normalized frequency, N_Zerocrossing is the zero

Implementation with a DSP

DPLL and LIA algorithms were implemented in the interrupt routine of the DSP. The main program was left to data conversion and exchange with a PC that acts as a user interface. Fig. 10 shows the implementation of the LIA.

Performance

Here we present some useful definition of the LIA. ‘Full scale signal’ means the input signal that produces the full scale output at the DC output amplifier.

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Sensitivity. It is the RMS amplitude of a input sine (at the reference frequency) which result in a full scale DC output.
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Overall gain. It is the ratio of the full scale DC output to the sensitivity.
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Gain distribution. It is the distribution of the overall gain between AC gain before the multipliers and DC gain following the multipliers.
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Conclusions

In this work we have presented a digital version of a LIA. Generally, LIAs are autonomous instruments and they are expensive. With a general purpose DSP based card, it is possible to develop and implement this useful instrument at low cost. The DSP card is plugged into a ISA-PC bus, and the host-PC acts as a user interface. The drawback is the stereo data acquisition card specifications (20 kHz bandwidth, ±3.5 V-input range). Of course the hardware of the system could be improved to reach

Acknowledgements

The authors acknowledge financial support from Secretarı́a de Ciencia y Tecnologı́a (SECyT), Universidad Nacional de Córdoba (UNC) and Agencia Córdoba Ciencia (CONICOR), Córdoba, Argentina. We would also like to acknowledge the assistance of Ph.D. Walter Lamberti.

Javier Gaspar was born in S. S. de Jujuy, Argentina in 1969. He received the degree in Electronic Engineer in 1996 from the Universidad Nacional de Córdoba, Argentina. His current research interest include PC based Instrumentation, DSP and Real Time Processing.

References (4)

R. Higgin's
Digital Signal Processing in VLSI
(1990)
E.A. Lee et al.
Digital Communication
(1992)

There are more references available in the full text version of this article.

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Carlos Marqués was born in Córdoba, Argentina in 1947. He received the degree in Electronic Engineer in 1970 from the Universidad Católica de Córdoba, Argentina. His current research interest include PC based Instrumentation and Microelectronics.

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