Scalable ATM network interface design using parallel RISC processors architecture

Abstract

In this work, a high-speed scalable ATM network interface has been designed and simulated. The interface has two processing engines, one for the transmission and the other for receiving side. Two specialized single-issue RISC cores supported with three stages pipeline and forwarding engine, have been used to process the network interface functions and ATM protocols. In addition, the interface architecture has Content Addressable Memory, five First-In-First-Out buffers, two simple Direct Memory Access units, two dual-port RAM, host interface, and transmission lines interface. The performance evaluation of the network interface has been measured through the development of a VHDL-based cycle accurate simulator. The results have shown that such network interface is scalable and could support a wire-speed of 2.4 Gb/s when the RISC cores run at a clock rate of about 170 MHz.

Introduction

In the early stages of the high-speed network interfaces development, the design approach using off-the-shelf components integrated over the Printed Circuit Boards were used for implementing network interface cards [1]. The technology advances in chip designs and specifically in the area of Application Specific Integrated Circuits (ASICs) have made possible to integrate most, if not all, discrete components that required for network interface on a single chip [2]. Clearly, using ASICs in implementing network interfaces have reduced design cost and complexity; improve their reliability, and performance. Generally, these ASICs used specialized engines to process the interface and the protocols functions. Such specialized engines are constructed from sequential machines and discrete logic [3], [8], [9]. However, using the specialized engine has made the design change costly and time consuming. Such design change could occur often when it is required to change the communications protocols, adding new network interface functions, or enhancing the existing one.

The network interfaces designers avoid using the general purpose embedded processor cores in their ASICs. Different reasons are behind such decision, such as the specialized engines could run at higher clock rates than the embedded cores and do not occupy a large space on the ASIC chip. In addition, licensing the commercially available embedded cores in order to be used as the processing cores on the ASICs is costly and they are not designed specifically for high-speed network interface processing. These cores, however, have some important advantages such as providing an easy way to support the interface to adapt a protocol revision or even a new protocol by changing the software that processed by the interface's engine. In addition, using these cores would lower development cost and simplify interface's datapath [3].

The recent advances in the area of CAD tools and the Hardware Description Language has made developing a specialized embedded RISC core, and other components required for the network interface design, a relatively easy task. In addition, the new development in the area of System-On-Chip technology has made easy to accommodate all the hardware required for the network interface in one chip [4]. In addition, there are many cost effective embedded cores that become available and can be easily ported to a network interface chip. These advances have directed this research to investigate the evaluation of the use of RISC embedded cores in high-speed network interfaces design and to measure their performance and scalability for high-speed network interfaces applications.

This work is focused on evaluating the use of simple RISC cores in performing the processing required by the high-speed network interfaces. We have used RISC cores in Asynchronous Transfer Mode (ATM) network interface design. Generally, the ATM network interfaces supports wide range of wire speed. Conducting ATM protocols processing using RISC cores will show the performance of using such cores in supporting the ATM scalable network interfaces. The RISC core performance is measured for performing the processing of the network interface functions, such as Segmentation and Reassembly (SAR) functions. Such functions are considered as a real processing challenge, especially when the network interfaces support high-speed communications lines.

This paper organized as follows: Section 2 discusses the architectural consideration for the design of the ATM network interface. In Section 3, the RISC core architecture has been investigated and the core design has been highlighted. The SAR functions processing are discussed in Section 4. Section 5 describes the approach that we have used to improve the data movement processing. The VHDL-based cycle-accurate simulator has been discussed in Section 6. The simulation results of the network interface that support different wire-speeds and the system-level simulation have been discussed in Section 7.