An efficient VLSI implementation of IDEA encryption algorithm using VHDL
Introduction
Recently, the number of individuals and organizations using wide computer networks for personal and professional activities has increased a lot. Among them, there are several applications highly sensitive to data security such as commercial exchange on the Internet and smart cards [1], [2]. A cryptographic algorithm is an essential part in network security. A well-known cryptographic algorithm is the Data Encryption Standard (DES) [3], [4], which is widely adopted in security products. However, serious considerations arise from long-term security because of the relatively short key word length of only 56 bits and recently from the highly successful cryptanalysis attack [4].
Another cryptographic algorithm is International Data Encryption Algorithm (IDEA) [4], [5], which is considered one of the most important post-DES cryptographic algorithms due to its high immunity to attacks [6], [7]. The IDEA algorithm overcomes the problems of DES algorithm. IDEA is highly secure. It would take one billion computers testing one billion combinations per second, 10,000 billion years to crack the code (2128 variants)-longer than the universe has existed [4]. It can be widely used in audio and video data for cable TV, pay TV, video conferencing, sensitive financial and commercial data, e-mail via public networks' transmission lines via modem, router or ATM link, and smart cards.
Many researchers have implemented the IDEA algorithm. Curiger et al. [8] has implemented a chip which is the first silicon block encryption device that can be applied to on-line encryption in high-speed networking protocols like ATM. With a system clock frequency of 25 MHz, this device permits a data conversion rate of more than 177 Mbps. Salomao et al. [9] has implemented a single round of IDEA on one chip, and it operates at a worst case clock frequency of 30 MHz producing a throughput of 424 Mbps. Qin et al. [10] has also implemented a chip whose maximum clock time period and throughput reported are 8 and 133 Mbps, respectively.
In this paper, we present a VLSI implementation of the IDEA block cipher using VHDL using AMI 0.5 process technology [11] standard cells. We have optimized the modulus multiplier and exploited the temporal parallelism available in the IDEA algorithm. In our implementation, the subkeys are generated internally once the original key is fetched. This key is retained unless a new key is used for encryption. This implementation does not employ additional RAM to store the subkeys, which is a significant improvement in area. Our chip contains the same eight units, and each unit can execute one round of the algorithm. Using pipelined design, eight rounds of the algorithm are executed in parallel in a chip. Our implementation operating at 10 MHz achieves a throughput of greater than 700 Mbps, which is several times higher than previous implementations.
The rest of the paper is organized as follows. Section 2 describes the IDEA cryptographic algorithm. Section 3 describes the architecture of the cryptographic chip, explaining the details of the different building blocks. Section 4 compares the performance of our implementation to earlier ones. Finally, Section 5 concludes the paper.
Section snippets
The IDEA cryptographic algorithm
In this section, we will briefly introduce the IDEA algorithm. IDEA is a symmetric, block-oriented cryptographic algorithm. It operates on 64-bit plain text blocks and uses 128-bit keys, which makes it practically immune to brute-force attacks. IDEA is based upon a basic function, which is iterated eight times. The first iteration operates on the input 64-bit plain text block and the successive iterations operate on the 64-bit block from the previous iteration. After the last iteration, a final
The VHDL implementation of IDEA
The goal of this implementation is to achieve the highest possible throughput. After a careful evaluation of the basic building blocks, we have established an eight-stage pipelined data path containing one round in each stage, each operating on a different data set. We have used the bottom-up design approach, implementing the elementary operations first before designing the final data path.
The design of multiplier is very crucial for the optimal performance of the chip. The time required for
Performance comparison
We have optimized the modulus multiplier and exploited the temporal parallelism available in the IDEA algorithm. Consequently, the performance of our implementation is comparable to earlier ones as shown in Table 1. Our data conversion rate is several times higher than other implementations considering clock frequency and the area of our chip is much smaller than others.
Next, we considered the effect of feature size scaling on the delay of the multiplier to compare our implementation with
Conclusion
In this paper, we have presented a VLSI implementation of the IDEA block cipher using VHDL using AMI 0.5 process technology standard cells. We have optimized the modulus multiplier and exploited the temporal parallelism available in the IDEA algorithm. The subkeys are generated internally once the original key is fetched. This implementation does not employ additional RAM to store the subkeys, which is a significant improvement in area. Our chip contains the same eight units, and each unit can
Madan Mohan Thaduri is working as an analog design engineer at Princeton Microwave Technologies in NJ, USA. His research interests include VLSI architectures, DSP systems and embedded programming. He has a Master's degree in electrical engineering from the University of Alabama in Huntsville. He can be contacted at [email protected].
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Cited by (0)
Madan Mohan Thaduri is working as an analog design engineer at Princeton Microwave Technologies in NJ, USA. His research interests include VLSI architectures, DSP systems and embedded programming. He has a Master's degree in electrical engineering from the University of Alabama in Huntsville. He can be contacted at [email protected].
Seong-Moo. Yoo is an associate professor of electrical and computer engineering department, the University of Alabama in Huntsville. His research interests include computer security, wireless networks, and parallel computer architecture. He has a PhD degree in computer science from the University of Texas at Arlington. He is a senior member of IEEE (computer society and communication society) and a member of ACM. Contact him at [email protected].
Rhonda Kay Gaede is an associate professor of electrical and computer engineering, the University of Alabama in Huntsville. Her research interests include computer architecture, VLSI design, and reconfigurable computing. She has a PhD degree in electrical engineering from the University of Texas at Austin. She is a member of IEEE (computer society), ASEE and ACM. Contact her at [email protected].