The rapid prototyping experience of an H.263 video coder onto FPGA

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Abstract

In this paper, the methodology used for prototyping an H.263 basic line video coder is explained. The coder is based on an architecture, which we have called MVIP-2, consisting of a set of specialized processors for the main tasks (transforms, quantizers, motion estimation and motion compensation) and a RISC processor for the scheduling tasks.

The design has been written in synthesizable Verilog and fully tested with hardware–software co-simulation using standard video sequences. All modules except the RISC have been synthesized and fitted onto an FPGA. The prototype has been tested in real-time using a commercial board with the RISC and the FPGA, a pattern generator emulating a video camera to generate the input sequences and a logic analyzer to test the H.263 output stream.

We have used a classic design methodology with some improvements in order to carry out rapid system prototyping. With this improved methodology, a prototype can be obtained early in the design cycle allowing the debugging of some hardware and software components permitting others to be designed at the same time.

In this paper we explain how this methodology has been applied to a complex design (MVIP-2). Despite some details being specific to this design, the main aspects of the methodology can be applied to other designs.

Introduction

In the last 10 years, the evolution of the digital technologies, together with the establishment of a set of standards widely followed by the industry, such as MPEG-2 [1], MPEG-4 [2] and H.263 [3], has allowed the development of a wide range of video applications: digital TV, HDTV, VoD, videophone, videoconferencing, etc.

The applications implemented in low rate channels, e.g. videophone, use low-resolution formats such as CIF (Common Intermediate Format: Spatial resolution of 360×288 pels and temporal resolution of 30 frames/s). Even so, the available bandwidth is usually rather lower than that needed for working with a minimum level of performance.

The image compression techniques can drastically reduce the bit-rate needed to encode the digital video signals. Although a large quantity of useful techniques have been reported, nearly all applications are based on the hybrid encoding scheme shown in Fig. 1, which uses the discrete cosine transform (DCT), quantization (Q) and motion estimation and compensation (ME/MC) among other techniques to carry out a reduction in the spatial and temporal redundancies existing in any natural sequence of images.

MVIP-2 is a flexible architecture which implements an H.263 video coder based on the hybrid encoding loop shown in Fig. 1. The architecture is made up of a core RISC that controls the scheduling of a set of specialized processors that implement the coder loop. Our medium term goal is to offer this architecture as a flexible IP core useful for inclusion in H.263, MPEG-2 or MPEG-4 video coder SoC, as this scheme, with some differences, is the basis of these coders. In this context, a prototype of the design allows early debugging of both hardware and software and also early validation of the design in a real environment. At present, the main vendors [4], [5] offer up to 8 Million-gate FPGAs that are suitable for prototyping complete large systems such as MVIP-2. Instead, as a cost-effective solution, we use the HSDT200 development board [6], a system that includes a RISC processor, and a 400,000 gate FPGA.

The design of MVIP-2 has been carried out using a classic methodology based on Hardware Description Languages (HDLs) and logic synthesis, improved with rapid system prototyping techniques that allow a prototype to be obtained at an early stage in the design cycle. The prototype can be used as a platform for debugging both the hardware and software parts of the design, allowing an early detection of faults that are difficult or not possible to detect in simulation.

A detailed description of MVIP-2 architecture, hardware and software, and a comparison with other developments can be found in [7]. This paper, on the other hand, is focused on the prototyping methodology of the MVIP-2 H.263 coder using the HSDT200 platform; our methodological approach to rapid system prototyping is described and also the application of this methodology to our design is explained. In the rest of the paper, a brief review of H.263 video coding architectures is presented in Section 2. Section 3 gives a short description of the MVIP-2 architecture. Section 4 is devoted to explaining the methodology and details of prototyping. In Section 5 the results obtained and the status of the project are explained. Finally, some conclusions on the methodology are set out in Section 6.

Section snippets

H.263 video encoding architectures

Over the last 4 years many implementations of H.263 video coders have been presented in international publications. The implementations based on general purpose microprocessors, including PCs or workstations [8] reach only realtime for images up to QCIF (Quarter CIF) so many researchers focus their design effort on efficient coder architectures.

A first group of architectures is based on special microprocessors such as DSPs, vector parallel processors or multiprocessors. As more significant

The MVIP-2 architecture

In this section only a brief description of MVIP2 is presented (a detailed description of MVIP2 architecture can be found in [7]) as the aim of this paper to focus on the design methodology.

The design methodology

In the development of the MVIP-2, a classic design methodology based on HDL and logic synthesis has been followed:

  • (a)

    The starting point is a text document which details the main hardware blocks and their functionality, the external interfaces, the data-flow between blocks, the scheduling and the software functionality. From the initial specifications a Verilog description for all modules except the RISC is written. A first version for the software is also developed in C language.

  • (b)

    The design is

Results

An RTL description of MVIP-2 and a first version of the software for the RISC processor have been obtained. Exhaustive hardware–software co-simulation functional tests with both ad-hoc and standard test sequences have been performed. For example, Table 1 shows the peak signal to noise ratio (PSNR) and the output bitrate obtained for the first 10 images of the QCIF Miss America sequence. Fig. 13 also shows the original and reconstructed first and seventh images of the sequence.

This functional

Conclusions

In this paper the design and prototyping of a flexible architecture that implements a basic-line H.263 encoder has been presented. The design has been carried out using a classic methodology based on HDL and logic synthesis, which has been improved with rapid system prototyping techniques.

With this improved methodology three main advantages have been obtained:

  • (a)

    An HDL testbench with the same structure as the final testbench was obtained early in the design cycle. With this testbench, initial

Acknowledgements

This work is being supported by grant TIC990927 from the Comisión Interministerial de Ciencia y Tecnología (CICYT) of the Spanish Government.

Matías Garrido received the Ingeniero de Telecomunicación degree with honors in 1996 and the Doctor Ingeniero de Telecomunicación degree with summa cum laude in 2004, both from the Universidad Politécnica de Madrid. Since 1986 he has been a member of the faculty of the E.U.I.T. de Telecomunicación of the U.P.M., and since 1987 he has been Associate Lecturer at the Department of Electronic and Control Systems. He is a founder member (in 1996) of the Electronic and Microelectronic Design Group

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Matías Garrido received the Ingeniero de Telecomunicación degree with honors in 1996 and the Doctor Ingeniero de Telecomunicación degree with summa cum laude in 2004, both from the Universidad Politécnica de Madrid. Since 1986 he has been a member of the faculty of the E.U.I.T. de Telecomunicación of the U.P.M., and since 1987 he has been Associate Lecturer at the Department of Electronic and Control Systems. He is a founder member (in 1996) of the Electronic and Microelectronic Design Group (GDEM), participating in design projects from the Spanish and European industry as well as university projects. His areas of interest are electronic digital design, video coding and digital video broadcasting.

César Sanz received the Ingeniero de Telecomunicación degree with honors in 1989 and the Doctor Ingeniero de Telecomunicación degree with summa cum laude in 1998, both from the Universidad Politécnica de Madrid. Since 1984 he has been a member of the faculty of the E.U.I.T. de Telecomunicación of the U.P.M., and since 1999 has been Associate Professor at the Department of Electronic and Control Systems. In addition, he leads the Electronic and Microelectronic Design Group (GDEM) involved in R&D projects with Spanish and European companies and public institutions. His areas of interest are microelectronic design applied to image coding, digital TV and IP-data transmission over digital broadcasting networks.

Marcos Jiménez received the Ingeniero de Telecomunicación degree in 2001, from the Universidad Politécnica de Madrid. He has been a member of the Electronic and Microelectronic Design Group since 2000 and at present also works as a software developer at SIDSA. His areas of interest are real-time video coding hardware implementations and IP transmission over digital television networks.

Juan M. Meneses received the Ingeniero de Telecomunicación degree in 1977 and the Doctor Ingeniero de Telecomunicación degree with summa cum laude in 1985, both from the Universidad Politécnica de Madrid. Since 1989 he has directed a research group in digital architectures for image and video processing. At the present, he is a full professor at the Electronics Engineering Department and senior scientist at GDEM.

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