Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs

Abstract

We propose a cost-efficient concurrent error detection (CED) scheme for finite state machines (FSMs) designed for implementation with embedded memory blocks (EMBs) available in today’s SRAM-based FPGAs. The proposed scheme is proven to detect each permanent or transient fault associated with a single input or output of any component of the circuit that results in its incorrect state or output. The experimental results obtained using our proprietary FSM synthesis tool show that despite the heterogeneous structure of the proposed CED scheme, the overhead is very low. For the examined benchmark circuits, the circuitry overhead in terms of extra EMBs is in the range of 6.3–56.3%, with an average value of 27.2%, whereas the combined overhead (EMBs and logic cells) calculated under pessimistic assumptions is in the range of 20.7–63.8%, with an average value of 32.2%. This compares favorably with the earlier proposed solutions applicable to conventional FSM designs based on gates and flip–flops for which an overhead exceeding 100% is quite typical.

Introduction

As technology advances to the deep submicron level, digital circuits have become increasingly more susceptible to faults, especially soft (transient) faults induced by various types of radiation. Error failure rates caused by such faults will soon become unacceptable even for mainstream commercial applications [12]. Therefore, there is an increasing interest in designing digital systems so that to make them fault-tolerant, i.e. to protect them against faults that occur during normal operation.

There are different ways to provide fault tolerance. Some of these methods are based on the concept of error masking and rely on massive hardware redundancy. Such methods, for example TMR (Triple Modular Redundancy), are very costly and can be afforded only for very critical applications. Alternative methods are based on on-line detection of errors and taking an appropriate “recovery” action (for example, precise identification of the faulty component and its replacement with spare resources available in the system). The key part of the latter techniques is effective concurrent error detection (CED).

Various CED schemes and the corresponding design techniques have been proposed for digital circuits and systems. Most of these schemes rely on information and hardware redundancy. However, schemes based on time redundancy, such as recomputation with shifted operands, alternating logic or multiple sampling of the outputs, can support error detection. In microprocessor-based systems, software-oriented concurrent error detection techniques can also be employed.

Most hardware redundancy based design techniques for concurrent error detection in digital circuits and systems presented in the literature assume that at some stage of design, a circuit is represented by a network of gates and flip–flips (or equivalent Boolean formulas) and that such a representation is then mapped onto standard cells. Under this assumption, the CED schemes and the corresponding design techniques have been proposed for:

• general combinational logic blocks and sequential subcircuits (implementing finite state machines – FSMs) [1], [6], [13], [14], [19], [27], [38], [40],

• specific functional units such as adders and ALUs [16], [28].

Other CED techniques have been proposed for alternative circuit implementations, in particular for:

• sequential circuits operating as microprogrammed control units [18], [39],

• PLA-based implementations of combinational and sequential circuits [10].

A number of CED schemes and design techniques have also been proposed for circuits implemented with SRAM-based FPGAs. Such solutions are of special importance for the following reasons:

• FPGA are becoming an implementation technology of choice for a large class of today’s digital systems, especially when low non-recurring engineering cost, short time-to-market or flexibility are crucial,

• SRAM-based FPGAs are particularly vulnerable to soft (transient) faults occurring during normal system operation.

The major source of soft (transient) faults and resulting errors in SRAM-based FPGAs are single event upsets (SEUs) induced by external radiation. SEUs affect both functional memory (flip–flops, embedded memory blocks) and configuration memory of an FPGA. Faults that affect the configuration memory can modify the function of LUTs and other programmable components and can also change the circuit interconnection structure [3], [4], [8], [35]. SEUs affecting the FPGA configuration memory are sometimes classified as permanent faults or, more precisely, recoverable permanent faults [3], as they can be corrected by reloading the configuration bit-stream of the FPGA device.

Memory cells, especially those in dense memory arrays, are more susceptible to radiation-induced faults than other logic components. Therefore, circuits implemented with SRAM-based FPGAs, containing a large number of memory arrays (functional and configuration memory) are more vulnerable to soft faults that occur during normal circuit operation than circuits implemented with other technologies.

One way to protect FPGA-based designs against faults that occur during normal circuit operation is to use radiation-hardened versions of FPGA devices which are based on special design of memory cells [30]. Such high-reliability components are, however, very expensive and not always available for the newest FPGA products. Therefore, solutions that are applicable to standard FPGA devices are of primary importance.

Various dedicated architectures and design techniques to deal with errors that occur during normal operation of FPGA-based systems, especially with SEU-induced errors, have been proposed. These include:

• triple modular redundancy (TMR), usually combined with readback and partial correction of configuration memory or full reloading of the configuration memory (the process usually referred to as scrubbing) [5], [11], [35],

• periodic readback for checking the state of the user memory and sections of configuration memory (single frames) augmented with CRC checksums, combined with partial reloading of configuration memory and user memory [2], [3],

• duplication with comparison (DWC), combined with timing redundancy for fault identification or with reconfiguration based on precompiled configurations [17], [20],

• implementation of schemes based on concurrent error detection/correction codes using FPGAs [24], [25], [37],

• adjustments of on-line testing techniques developed for circuits represented by a network of gates and flip–flops (typically implemented with standard cells) through post-synthesis modification of the network [7], [8],

• dedicated synthesis procedure for self-checking logic implemented with 2-LUT programmable logic blocks (the two LUTs produce complementary outputs) [23],

• using special placement and routing algorithms [33],

• using new basic FPGA components (SRAM-cells) optimized for soft errors [34],

• using new structures of FPGA logic and routing components that facilitate checking the FPGA configuration bits, sometimes combined with appropriate coding techniques for error detection and correction [36], [41].

In this paper, we deal with concurrent error detection (CED) for sequential circuits – finite state machines (FSMs) implemented using embedded memory blocks of FPGAs. The development of CED schemes for such circuits is interesting for the following reasons:

• embedded memory blocks are available in almost all today’s SRAM-based FPGAs,

• embedded memory blocks can be effectively used to implement FSMs [9],

• architectural features of FPGAs with embedded memory make the implementation of CED in such devices relatively cost-efficient, especially when compared with other types of devices.

The paper is structured as follows: In Section 2, concurrent error detection schemes proposed for various structures of sequential circuits are described. Section 3 presents specific problems associated with an FSM implementation using embedded memory blocks of an FPGA. The proposed concurrent error detection scheme for such an implementation is described in detail in Section 4. In the subsequent section, it is proven that the proposed scheme guarantees the detection of all faults in the assumed fault model. Then, in Section 6, for a set of benchmark FSMs, the cost of implementing the proposed CED scheme in terms of extra logic components (embedded memory blocks and programmable logic components) is estimated and compared with the earlier proposed solutions applicable to conventional FSM designs based on gates and flip–flops. Finally, Section 7 summarizes our contribution.