Simulation based verification of energy storage architectures for higher class tags supported by energy harvesting devices

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Abstract

Enhanced RFID tag technology especially in the UHF frequency range provides an extended functionality like high operating range and sensing and monitoring capabilities. Such complex functionality requires extended system structures including data acquisition units, real time clocks and active transmitters that cause a high energy consumption of the tag and require an on-board energy store (battery). Since the lifetime is a key parameter for the reliability of an RFID system, the energy budget of the higher class tag has to be as balanced as possible. This can be achieved by using energy harvesting devices as additional power supplies. The PowerTag1 project and thus this paper propose special energy storage structures, which interface energy harvesting devices and deal with their special requirements to be used with battery-driven higher class UHF RFID tags. Different implementation variants of such structures are compared by using accurate simulation models of various parts of the system. The results of the simulation are compared to provided manufacturer performance parameters of a state-of-the-art higher class UHF RFID system.

Introduction

The next generation of UHF RFID tags (called higher class UHF RFID tags – HCT [2]) provides extended functionality in terms of independent sensing and monitoring, high communication range and large memory areas. Such functionality requires a continuous tag operation, which is not possible if the tag is solely powered by the reader as in the former pure passive UHF RFID systems [3]. Thus, an on-board energy supply is necessary, which forces the renaming of the previously called passive UHF RFID technology to semi-passive and active technology. This change in the tag architecture causes new issues in the area of UHF RFID: the limited operational lifetime and the need of long lasting power saving techniques. The energy, which can be stored on a tag is limited by the state-of-the-art energy storage technology and so even with profound power saving techniques the achievable lifetime is often dissatisfying. The proposed way to solve this issue is to harvest energy from the environment by energy harvesting devices, which due to a massive research and development are available in small sizes and high efficiencies satisfying limitations of UHF RFID tags. As the energy converted by such devices comes from the environment, it is generally unpredictable, discontinuous and unstable [6].

This work presents novel, special developed energy storage architectures dealing with those special requirements by proposing novel interface- and energy storage structures, which are able to store and handle the largely varying provided power. Fig. 1 shows the structure of an active higher class tag including energy harvesting device(s) and the energy storage architecture. It divides the tags architecture into three subgroups: (i) the communication and data processing subsystem, which deals with the communication and processing of the measured data; (ii) the sensing subsystem, which includes sensors and data acquisition units; (iii) the power subsystem, which is the key focus of this paper and describes power supply and energy storage modules of the tag.

Section snippets

Related work

In [4] special energy storage architectures are presented, which use environmental radio frequency fields for supplying mobile phones. The key goal of the project is to design an energy storage architecture being able to convert the scavenged very low power to a level, which can be used to charge the phones batteries. Such conversion circuitry is one part of the energy storage structures proposed in this paper. In [11] an energy storage architecture including a rechargeable battery interfacing

Novel energy storage architecture

The energy storage architecture includes all the mandatory modules for supplying the higher class tag. It includes special interface structures interfacing the energy harvesting devices and energy storage devices dealing with their special requirements (unstable energy supply). Additionally included are buffer structures buffering the peaks of the power consumption caused by the various activities of the higher class tag (active transmission…).

Simulation model for the verification of energy storage architectures

To evaluate the performance and benefits of all the three implementation variants described before and to compare them to a state-of-the-art higher class tag which is powered by just a single-use primary battery, a simulation model has been developed. This simulation model is described in the following sections.

Simulation model verification

As the battery model is the most complex and at the same time most critical part of the simulation system defining the accuracy of the whole model, the verification of its accurateness is essential to be able to make a statement on lifetime improvements. This section describes simulations and related results with the goal to verify the simulation model accurateness with the focus on the battery. In a first step simulation results are compared with real battery data sheet parameters. As the

System simulation results

After the verification of the accurateness of the simulation model, the implementation variants 1, 2 and 3 (Section 3.2) are compared under various aspects by simulating the complete system including energy harvesting device and the current load profile of the higher class tag. This allows to choose the best implementation method for the energy storage architecture.

Conclusion

The simulation results presented in this paper show that the achieved lifetime is significantly improved by the used implementation variants. This allows to reduce the capacity of the on-board energy storage significantly, which saves size and weight or allows to improve the computational capabilities of the tag achieving the same lifetime. As demonstrated in this paper, the verification method (based on simulation and modeling) facilitates a pre-testing of various energy storage architectures

Acknowledgement

Special thanks to Identec Solutions AG for providing the required active UHF RFID equipment to perform the measurements presented in this paper.

Alex Janek, a PhD student at the Institute for Technical Informatics, Technical University of Graz started his PhD about system modeling of higher class tags equipping energy harvesting devices in October 2005. His Diploma thesis about Hardware-in-the-Loop simulation of UHF RFID Tags was still focusing on a similar topic. The PhD work is done in cooperation with CISC Semiconductor Design+Consulting GmbH, where Alex Janek – being a member of the business unit RFID+RFComm – is involved as Systems

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Alex Janek, a PhD student at the Institute for Technical Informatics, Technical University of Graz started his PhD about system modeling of higher class tags equipping energy harvesting devices in October 2005. His Diploma thesis about Hardware-in-the-Loop simulation of UHF RFID Tags was still focusing on a similar topic. The PhD work is done in cooperation with CISC Semiconductor Design+Consulting GmbH, where Alex Janek – being a member of the business unit RFID+RFComm – is involved as Systems Engineer and project leader in customer projects related to his research activities, mainly the simulations of higher class UHF RFID tag architectures. The research work is done in close relation to ongoing standardization activities in ISO and EPCglobal especially supporting the introduction of the new RFID technologies into existing Standards (e.g. ISO18000-6REV1).

Christoph Trummer received his MSc. degree in Telematics from Graz University of Technology. Currently he is with the Institute for Technical Informatics where he is working towards his PhD degree. His main research interests are energy harvesting, energy sources, power awareness and codesign/simulation of systems-on-chip.

Christian Steger received in 1990 the Dipl.-Ing. degree and in 1995 the Dr.techn. degree in Electrical Engineering, Graz University of Technology, Austria. He graduated from Export, International Management and Marketing course in June 1993 at Karl-Franzens-University of Graz. He worked as a Research Engineer from 1990 to 1991 and since 1992 he has been working as an assistant professor at the Institute for Technical Informatics, Graz University of Technology. In summer 2002, he was a visiting researcher at the Department of Computer Science at the University College Dublin (Irland). He heads the HW/SW codesign group (8 PhD students) at the Institute for Technical Informatics. His research interests include embedded systems, HW/SW codesign, HW/SW coverfication, SOC, power awareness, smart cards, UHF RFID systems, multi-DSPs. He is currently working with industrial partners on heterogeneous system design tools for system verification and power estimation/optimization for RFID systems, smart cards and wireless sensor networks. Christian Steger has supervised and co-supervised over 73 master theses and co-supervised 8 PhD students, and published more than 70 scientific papers as author and co-author. He is a member of the IEEE and of the VE (Austrian Electrotechnical Association). He was also a member of the organizing committee of the Telecommunications and Mobile Computing Conference 2001, 2003, and 2005.

Reinhold Weiss is a Professor of Electrical Engineering (Technical Informatics) and head of the Institute for Technical Informatics at Graz University of Technology, Austria. He received the Dipl.-Ing. degree, the Dr.-Ing. degree (both in Electrical Engineering) and the Dr.-Ing.habil. degree (in Realtime Systems) from the Technical University of Munich in 1968, 1972 and 1979, respectively. In 1981, he was as a Visiting Scientist with IBM Research Laboratories in San Jose, California. From 1982 to 1986 he was Professor of Computer Engineering at the University of Paderborn (Germany). He is author and co-author of about 170 scientific and technical publications in Computer Engineering. For e&i (Elektrotechnik & Informationstechnik, Springer-Verlag) he served several times as a guest editor for special issues on Technical Informatics and Mobile Computing, respectively. In 2001 and 2003, he organized two Workshops on Wearable Computing. His research interests focus on Embedded Distributed Real Time Architectures (parallel systems, distributed fault-tolerant systems, wearable and pervasive computing). He is a member of the International Editorial Board of the US- journal “Computers and Applications” (ISCA). Further, he is a member of IEEE, ACM, GI (Gesellschaft fr Informatik, Germany), and VE (sterreichischer Verein fr Elektrotechnik, Austria).

Josef Preishuber-Pfluegl is CTO and Business Unit Manager RFID & RF Comm of CISC Semiconductor Design+Consulting GmbH. Starting on 125 kHz reader concepts Josef Preishuber-Pfluegl got involved in radio frequency identification (RFID) in 1995 with his Master thesis on LF (125 kHz) reader demodulator at Graz University of Technology in Austria. He worked in several areas of RFID engineering and product management for system design, reader, tag and tag ASIC development covering all the frequencies of passive RFID. Currently, he is an active participant in several standardization groups in the ISO/IEC JTC1/SC31 area, convener of the ISO/IEC JTC1 SC31 WG3/SG1 for RFID performance+conformance. Furthermore, he is a project editor for the ISO/IEC 18000-6. Furthermore, he is also deeply involved in the EPCglobal work. Inside CISC, he set up the BU RFID+RFComm with its major activities in modeling, simulation, design and evaluation of RFID systems and RFID applications for LF, HF and UHF. The major focus in RFID system design is to support product and system design with simulation and measurement tools. This includes a full simulation environment for EPCglobal UHF Class 1 Generation 2-based application considering protocol, identification software and detailed RF aspects.

Markus Pistauer received his Degree in Electrical and Electronic Engineering. In 1995, he obtained his Ph.D. degree in Electronic and Control Engineering, Graz University of Technology, Austria. From 1988 to 1990 he worked as a Software Engineer at Siemens AG, Frankfurt. From 1989 to 1991, Software Consultant at SPC Computer Training Ges.m.b.H., Vienna; in 1991, as a Research Engineer at the Department for Sensoric, Joanneum Research Forschungsgesellschaft m.b.H., Graz; from 1991 to 1995, as an Assistant Professor at the Department of Electronics, Graz University of Technology; from 1995 to 1999, as a Research and Design Application Engineer at Siemens Design Center for Microelectronics in Villach/Austria; and from 1995 to 1998, as a Senior Lecturer for Electronic Engineering and Computer Science at Carinthia University of Applied Sciences. In 1995, he headed the international and national research projects in the area of CAD/CAE methods for integrated circuit design; in 1997, he was a judicial approved assessor for electronics and software; in 1999, he headed the consultancy office for IT and computer science; in 1999, he laid the foundation of CISC Semiconductor Design+Consulting GmbH; in 1999, he was the CEO of CISC Semiconductor. He was also a Member of IEEE and of the international program committee for conferences like “Informationstagung fr Mikroelektronik”, “IASTED International Conference on Modelling, Identification and Control”, “International Conference on Computer Systems and Applications”, and he was the author and co-author of more than 40 publications.

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This project has been supported by Austrian government under the Grant number 811854.

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