Characterizing asynchronous variable latencies through probability distribution functions

Abstract

Asynchronous systems are attracting the interest of the designer community because of several useful features for sub-micron technologies: process-variation tolerant, low-power, removal of the clock tree generation, etc. One of the main problems for the simulation of these systems is the variable computation delays of their modules, that compute as fast as possible under the actual conditions of the system. This behavior complicates the high-level simulation of such systems and it is the main reason for the lack of simulation tools devoted to asynchronous microarchitectures. In this paper we present a modeling method useful for this kind of systems that describes the variable computation delay of an asynchronous circuit by using probability distribution functions. This method is deployed in an architectural simulator of a 64-bit superscalar asynchronous microarchitecture where the computation delay of each one of the modules of the microarchitecture was characterized through a probability distribution function. The experimental results show that the asynchronous behavior is successfully modeled, and the architectural simulations of standard benchmarks is affordable in terms of wall-clock simulation time.

Introduction

Each successive technology is aggravating the well-known inconvenience of synchronous systems, that is, the need of over-designing the system to satisfy design constraints – about performance, power-consumption or device reliability under any corner conditions of process, voltage, temperature and on-chip-variations – in order to meet yield rates. Traditional techniques for minimizing design exposure to process and environmental variations are quickly becoming difficult to implement and consume an increasingly large portion of the microprocessor design.

As a result, the interest on asynchronous systems in the community of circuit designers is growing, i.e. [1], [2]. These circuits have a number of interesting inherent properties that solve some of the problems of synchronous designs:

• High performance [3], [4]: the global circuit performance of fully asynchronous systems corresponds to the performance of the average case. In asynchronous systems a new computation starts immediately after the previous has finished [5].

• Robustness towards variations on supply voltage, temperature and fabrication process [6], [7]: the functionality is designed to be independent from the timing, which allows the circuit to compute as fast as possible under any temperature, process and voltage corner.

• Modular design [8], [9]: the local timing and the communication protocol interfaces allow designers to create modular systems, even based on templates or asynchronous IP cores.

• Absence of clock distribution problems: there is no global clock signal in the system.

Nevertheless, there are two main drawbacks when designing asynchronous systems.

First, the control logic that implements the handshaking between asynchronous circuits usually represents an overhead in terms of silicon area, delay and power consumption. But, as shown in [3], [10], the overhead of the control logic may be hidden or compensated.

Second, there is a lack of CAD tools devoted to asynchronous circuits. Despite many CAD tools and algorithms for synthesis of asynchronous systems, i.e. [11], [12], [13], are currently available, there are few tools related to architectural simulation of asynchronous systems.

One of the main obstacles for the architectural simulation of asynchronous circuits and, therefore, for the development of simulation tools, is the data-dependency of the computation delays. The delay due to the computation may be different for each incoming data on an asynchronous circuit because it computes as fast as possible without any timing constraint. Up to our knowledge, there are not reported methods in literature related to the data-dependent characterization of the variable computation delay applied to the architectural simulations of asynchronous processors.

The simulation of this kind of systems requires firstly a method that enables, in a cost-effective way, both in terms of memory requirements and computing power of the simulation infrastructure, the characterization of asynchronous modules with data-dependent computation delays; and secondly, a tool able to simulate a processor whose modules are asynchronous circuits.

Hence, the main contributions of this paper are:

• A modeling method based on probability distribution functions (PDF) that allows the cost-effective architectural simulation of complex asynchronous systems, and

• A tool that allows the simulation of an asynchronous Alpha 21264-like processor. This tool deploys the modeling method based on PDFs and permits to configure most of the parameters of the processor with the aim of studying the processor performance under standard workloads, typically SPEC2000 suite.

The rest of the paper is organized as follows. In Section 2 we review works focused on measuring the performance of asynchronous systems. In Section 3 we introduce the problem of characterizing and simulating the data-dependent behavior of asynchronous circuits. In Section 4 we detail the method followed to obtain the PDF from a sample of delays, and we show a statistical metric to prove the quality of the sample. In Section 5 we describe the implementation of the PDF characterization within an architectural simulator, and in Section 6 we verify the cost-effective and successful architectural simulation of a superscalar asynchronous microarchitecture. Finally, in Section 7 we present the conclusions and the future work.