Integrating real-time inter-task communication channels into hardware–software codesign
Introduction
Hardware–software codesign is a design technique that jointly addresses the creation of hardware and software components in a system on chip (SoC) system. Due to hardware–software codesign, an embedded system design makes extensive use of programmable architectures and requires engineers to consider hardware and software jointly in their design. One important procedure in hardware–software codesign is to partition the functional system specifications into hardware and software components [1]. Typically, a partitioning process begins with an all software-partition and transforms some software components with performance bottlenecks into hardware components. Such a partitioning approach is expected to accelerate overall execution time of a system by implementing time-critical components in hardware rather than in software. After the partitioning process, a communication channel is required to exchange data between hardware and software components. Then, various hardware and software components are finally assembled through the communication channel to implement the entire system functionality. Therefore, even if the partitioning processing is optimized according to given some decision criteria, it is difficult to achieve the expected system performance without a well-designed communication channel between partitioned components.
The basic entities exploiting the communication channel are hardware and software components (or tasks), and shared messages between hardware and software tasks. To give more practical insights into hardware–software codesign on systems, the characteristics of tasks need to be further considered as follows: they need to be classified into periodic (or time-bounded) and aperiodic (or time-unbounded) in terms of the real-time constraints of tasks. An increasing number of real-time embedded systems are being connecting to the Internet. They dynamically generate new message patterns of deadline-driven applications, such as video and audio applications. This implies that the message generation patterns of applications need to be classified into periodic and aperiodic in terms of the real-time constraints of messages. In hardware–software codesign, the timing constraints of messages exchanged between tasks severely affect task scheduling, and thus, have to be taken into account. Additionally, aperiodic messages need to be quickly processed for fast response without missing periodic task and message deadlines. One possible approach to solve such a combined task and message scheduling problem is that message delay bounds and message generation patterns are assumed to be fixed and known when a real-time inter-task communication channel is designed and integrated into hardware–software codesign. Then, this approach attempts to solve the combined task and message scheduling problem by separating the timely delivery constraints of messages exchanged between tasks from the timing constraints of tasks. However, such a separation approach does not address the problem related to excessive message delivery delays when the corresponding tasks processing messages are not timely scheduled. The other possible approach presented in this paper is to schedule tasks and messages simultaneously.
In this paper, we propose a technique for a real-time inter-task communication channel that guarantees the deadlines of periodic tasks, as well as the timely delivery of periodic messages exchanged between tasks, while improving the average response time of aperiodic messages. The proposed real-time inter-task communication channel is composed of a unified inter-task communication interface between hardware and software tasks. The unified inter-task communication interface deals with three possible inter-task communication associations: software-to-software, software-to-hardware, and hardware-to-hardware task communication associations. In the unified inter-task communication interface, coarse-grained real-time processing is allowed at a level of task unit and fine-grained real-time processing is allowed at a piece of message frame unit. The combined task and message scheduling scheme takes advantage of a novel scheduling policy consisting of six decision rules. The scheduling policy incorporating six decision rules primarily meets the deadlines of periodic tasks and messages, and secondarily improves the response time of aperiodic messages without missing periodic task and message deadlines. Therefore, the proposed real-time inter-task communication channel is well-suited to dynamic, changeable message patterns generated by various applications and significantly improves system performance. The reminder of this paper is organized as follows: Section 2 presents the related work that motivates us to work on integrating a real-time inter-task communication channel into hardware–software codesign. Section 3 presents the framework of the unified inter-task communication interface developed in this research work. Section 4 presents the combined task and message scheduling scheme incorporating a scheduling policy that consists of six decision rules. In Section 5, the proposed technique is evaluated in terms of the minimal deadline miss ratio of periodic tasks and messages, and the average response time of aperiodic messages. Section 6 concludes this paper.
Section snippets
Related work
We discuss the existing sub-problems of hardware–software codesign for real-time embedded systems in terms of hardware–software codesign methodology, hardware–software partitioning and connectors for a unified inter-task communication interface, and real-time task and message scheduling in hardware–software codesign. Lee et al. [2] state that few studies have examined the cost impact of a codesign decision in real-time embedded systems. Combining hardware and software technology can be used to
A framework for UIC interface architecture
In this section, we describe the overall framework for the design of the unified inter-task communication (UIC) interface. The UIC interface plays a role of a hardware–software connector in hardware–software codesign. With regard to the detailed implementation technique of the hardware–software connector in SoC systems, it is rare to find a practical implementation technique of designing the inter-task communication interface in the literature survey. The UIC interface we developed in this
Combined task and message scheduling scheme
We present an analytical framework that theoretically evaluates the performance of the combined task and message scheduling scheme proposed in this paper. The combined task and message scheduling scheme timely processes periodic tasks and messages to meet their deadlines, and quickly processes aperiodic tasks and messages for fast response without missing the periodic task and message deadlines. In Section 4.1, we describe key notations used in this paper and present a scheduling policy
Experiments
All the experiments of the proposed technique were carried out on the SoC platform based on the Altera’s Excalibur chipset, including the ARM922T core and up to 1 million gates of programmable logic [25]. The total execution time of all the experiments in this paper is 20,000 s. The development tools used in this paper are Quartus 6.0 for FPGA synthesis [26] and ADS (ARM Developer Suite) C Compiler 1.2 [27]. Increasingly the trend in embedded network/multimedia system design is to integrate all
Conclusion
We propose a technique for the real-time inter-task communication channel consisting of a combined task and message scheduling scheme, and a unified inter-communication interface termed the UIC interface. The UIC interface provides a flexible framework for the message frame exchange enabling bidirectional communications among any software and hardware tasks. The combined scheduling scheme presented in this paper aims to achieve efficient performance in terms of three objective goals: the
Sungwoo Tak is an associate professor in the School of Computer Science and Engineering at Pusan National University. He is also a research member at Research Institute of Computer Information and Communication at Pusan National University. He received a Ph.D. degree in Computer Science from the University of Missouri – Kansas City. His research interests include computer networks, wireless networks, software architecture, WDM optical networks, real-time systems, game theory, and Network
References (31)
- et al.
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture
(2004) - et al.
Synthesis steps and design models for codesign
IEEE Computer
(1995) - et al.
A survial kit: adaptive hardware/software codesign life-cycle model
IEEE Computer Magazine
(2009) - et al.
Efficient communication between the embedded processor and the reconfigurable logic on an FPGA
IEEE Transactions on Very Large Scale Integration Systems
(2008) - et al.
Program implementation schemes for hardware–software systems
IEEE Computer
(1994) - et al.
Architectural partitioning for system level synthesis of integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
(1991) - et al.
Integrating physical constraints in HW-SW partitioning for architectures with partial dynamic reconfiguration
IEEE Transactions on Very Large Scale Integration Systems
(2006) - et al.
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia
IEEE Transactions on Very Large Scale Integration Systems
(2006) - N.R. Metha, N. Medvidovic, S. Phadke, Towards a taxonomy of software connectors, in: Proc. of 22nd International...
- W. Forster, C. Kutschera, A. Steininger, K.M. Goschka, Automated generation of explicit connectors for component based...
SLOPES: hardware–software cosynthesis of low-power real-time distributed embedded systems with dynamically reconfigurable FPGAs
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems
Design of high-performance system-on-chips using communication architecture tuners
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems
Cited by (1)
Sungwoo Tak is an associate professor in the School of Computer Science and Engineering at Pusan National University. He is also a research member at Research Institute of Computer Information and Communication at Pusan National University. He received a Ph.D. degree in Computer Science from the University of Missouri – Kansas City. His research interests include computer networks, wireless networks, software architecture, WDM optical networks, real-time systems, game theory, and Network processor Design. He is the corresponding author of this paper.
Taehoon Kim is a doctoral student in the School of Computer Science and Engineering at Pusan National University. His research interests include Location-awareness, P2P, real-time embedded systems, wireless networking, and Network processor Design.
E. K. Park is a Dean of Research and Graduate Studies at the City University of New York, Staten Island. Prior to joining the City University of New York, he held the position of National Science Foundation Program Director in the Division of Computing and Communications Foundation (CCF) and the Division of Computer and Network Systems (CNS). He was a Professor in, and Chair of, the Department of Software Architecture (it became the Department of Computer Science and Electrical Engineering) at the University of Missouri. He was also a Research Scientist and Fellow at the Naval Research Lab in Washington, DC. He is the founder of the International Conference on Computer Communication (ICCCN) and the International Conference on Information and Knowledge Management (CIKM). He has served as Editor-in-Chief and Associate Editor of journals in his research areas. He also has served as General Chair and Program Chair of various IEEE and ACM conferences and workshops. He received a PhD degree in Computer Science from the Northwestern University. His research interests include software engineering, software architectures, software agents, distributed systems, objectoriented methodology, software tolerance and reliability, computer networks and management, optical networks, database/data mining, numerical computing, optimizations, and information/knowledge management.