An embedded multi-core biometric identification system
Introduction
A quick and accurate system of personal identification can be of tremendous importance to restrict the access to places or resources to legitimate users, by now, and particularly after 9/11, such systems are part of our daily life. Traditional identification means, either token-based (access cards, keys, etc.) or knowledge-based (passwords, PINs, etc.), may be subject to theft or discovery. However, these are not the only identification technologies available. Biometric systems help to identify people by exploiting their physiological or behavioural differences. These systems do not rely on reproducible information, and therefore they are not liable to the risks characterizing passwords and keys.
Among the various biometric parameters that can be used to identify a person, fingerprints are undoubtedly the most used, as they are easy to acquire and have been studied since the 19th century, indeed, fingerprint recognition systems can now be found into many commodity goods (such as notebooks).
Despite their long history, Automated Fingerprint Identification Systems (AFIS) [1], [2] still offer interesting challenges. More specifically, the time required to compare two fingerprints can become a problem if general-purpose computers are used, especially when the database to which we are comparing our sample is very large.
This is the main reason for the extensive work in the development of efficient dedicated architectures able to compare two fingerprints in a small fraction of the time needed by a general-purpose computer.
In this paper, we propose the FPGA architecture of a complete AFIS system. The Band-Limited Phase-Only Correlation [3], [4] algorithm is used to compute the matching scores between a new (input) fingerprint and each image contained in a database. Several computational cores can be hosted on a single chip computer together with a general-purpose processor. External memories are managed through DMA and can be dynamically configured and a bottleneck/scalability projection is proposed.
After a brief description of the state of the art, the algorithm will be illustrated in detail. The hardware architecture is also discussed, followed by a description of the software implementation used as a term of comparison. Then, the performance (both in terms of speed and accuracy) will be described, and some conclusions drawn.
Section snippets
Fingerprints
Typical fingerprints are characterized by an alternation of ridges and furrows (dark and light areas in Fig. 1); fingerprints are different for each individual, and each finger of the same subject has its own unique pattern. They are already formed in a 7 months fetus and they are not affected by surface abrasions, burns and cuts, since their original pattern is reproduced as the skin regenerates.
The different arrangement and shape of dermal fibers create several ridges and a precise papillary
State of the art
Fingerprint matching allows to understand whether two fingerprints belong to the same finger and has been studied since the 19th century. Such a long history favoured the development of many different computational techniques.
The traditional approach, directly linked to human experts matching techniques, involves the comparison between two sets of minutiae, which are generally characterized by position, orientation and type.
Minutiae are not the only characteristic points in the image space: for
The matching algorithm
The implemented algorithm is known as Band-Limited Phase-Only Correlation (BLPOC), proposed in [3], [4] and involves the following processing steps:
- 1.
The two fingerprints to be compared are enhanced (to improve the results of the following steps);
- 2.
One of the fingerprints is rotated by several angles, thus generating a number of fingerprints to compare the other with;
- 3.
The enhanced fingerprints are transformed using the two-dimensional Discrete Fourier Transform (DFT);
- 4.
The high-frequency components
Hardware implementation
In order to build an embedded system able to automatically recognize a single template among thousands, a proper elaboration power is needed, together with small-size and low-power consumption. This led us to choose the programmable logic technology for our project. The use of FPGA as low-cost embedded accelerators for scientific intensive applications is nowadays well established as one of the possible alternatives to provide enough computing power [22]. We decided to implement the matching
Speed
Our hardware implementation has been deployed on an Altera Stratix II 2S60 FPGA board [29] with 2 MB of synchronous RAM, 16 MB of DDR SDRAM and 16 MB of flash memory. The board could host two parallel matching elements running at 100 MHz, with a usage equal to 86% in terms of logic utilization and a power consumption around 2, 5 W. The realized computing unit performs a matching between two fingerprints in 660 μs, which is the total throughput for the 2 cores. Table 1 represents the compilation
Discussion
In Table 2 a list is proposed of different solutions proposed in literature and our solution. The table reports the algorithm used in the elaboration, the particular technology of the FPGA device and its usage, the elaboration speed, the power consumption (in this case since not always it is provided we specify the working frequency).
Generally speaking, it seems that the most common techniques deal with a fine grain image investigation concerning the extraction of singularities like as
Conclusions
In this paper an architecture for fast fingerprint matching was proposed, together with the results obtained through FPGA implementations. By using the novel BLPOC algorithm, the processor tries to evaluate the correlation between the subject’s fingerprint to be examined and a lot of templates stored in a database. This goal is obtained with a reasonable and adjustable accuracy (EER close to 6%).
The size of each template is 64 KB; considering the elaboration-times, the required memory bandwidth
Giovanni Danese is full professor of computer programming and computer architecture in the engineering faculty at the University of Pavia. His current research interests include parallel computing, special-purpose computers, and signal and image processing. Danese has a PHD in electronics and computer engineering from the University of Pavia. He is a member of the IEEE Society. Contact him at [email protected]
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Giovanni Danese is full professor of computer programming and computer architecture in the engineering faculty at the University of Pavia. His current research interests include parallel computing, special-purpose computers, and signal and image processing. Danese has a PHD in electronics and computer engineering from the University of Pavia. He is a member of the IEEE Society. Contact him at [email protected]
Mauro Giachero has a Ph.D and a 1st class Laurea degree with honors in computer engineering achieved at the engineering faculty of the University of Pavia. His current research interests include computer and microprocessor architectures, parallel computing, compilation techniques, and resource-constrained computing. Contact him at [email protected].
Francesco Leporati is associate professor of industrial informatics and computer architecture in the engineering faculty at the University of Pavia. His current research interests include automotive applications, FPGA and application-specific processors, embedded real-time systems, computational physics. Leporati has a PHD in electronics and computer engineering from the University of Pavia. He is a member of the IEEE and Euromicro Societies. Contact him at [email protected].
Nelson Nazzicari, PhD, is an electronic and computer engineer currently working on joint research projects between Microcomputer Laboratory at University of Pavia (Italy) and Centre for Secure Information System at George Mason University (Virginia). He’s mainly focusing on creating embedded, low-power high-performing hardware for pervasive computing and security related applications. Contacts: [email protected], [email protected].