Non-minimal, turn-model based NoC routing
Introduction
The Network-on-Chip (NoC) paradigm has emerged as a long-term on-chip communication solution for Multi-Processor System on Chip (MPSoC) [1] and Chip Multi-Processor (CMP) [2] micro-architectures. The most common NoC architecture is a mesh network consisting of a two-dimensional array of nodes (or tiles) located on mesh-connected grid points. Processors, memory devices and other modules are placed throughout the network and interface with local routers via a Network Interface (NI) unit. Each local router is connected to four neighboring routers in the north, east, south, and west directions, respectively. Moreover, within each router, buffers are provided for each input channel, and a cross-bar switch is used to route the incoming packets to an appropriate output port.
In NoC-based communication systems, the data packets are generally broken into a contiguous sequence of flow units known as flits. Transmitting a packet from a source to its destination requires a consecutive transmission of multiple flits over the same path. The path is chosen distributedly by applying the same routing algorithm at each router encountered by the packets en route to their destinations.
An efficient routing mechanism is essential in optimizing the performance of NoC-based communication systems [3], [4]. Generally speaking, the routing algorithms used in NoC applications can be categorized as either minimal routing algorithms or non-minimal routing algorithms. In the former case, the algorithm selects a minimal path between the source and the destination along the way (i.e., detours are not permitted). On the other hand, in the latter case, the algorithm may consider alternative non-minimal paths.
In NoC-based systems implemented using a packet switching approach, the routing resources (i.e., the channels and buffers) are reserved for a particular data packet until all of the flits belonging to that packet have been transferred. If the input port buffer of a neighboring router en route is full, the packet must wait at the present router until that input buffer is vacated. In other words, the channel occupied by the current packet is dependent on the input channel of the neighboring router. If the channel dependence of a set of paths leads to a circular dependence relation, none of the packets are able to proceed, and the so-called deadlock condition occurs.
A key strategy when developing deadlock-free routing algorithms is to ensure that cyclic channel dependence cannot occur. Toward this goal, several turn-model based routing algorithms have been proposed [5], [6]. In general, such models prohibit the packets from making specific types of turns so as to prevent the formation of cycles among them. As such, Glass and Ni [5] claimed that “routing algorithms that employ the remaining turns are deadlock free, livelock free, minimal or non-minimal, and highly adaptive for the network”.
However, despite the claim of [5] that turn models are applicable to both minimal and non-minimal routing paths, existing turn-model based algorithms, e.g., those based on the West-First, North-Last, and Negative-First turn models [5] or the Odd–Even turn model [6], are all constrained to the use of minimal routing paths. Moreover, Chiu [6] commented that “non-minimal paths are possible with the Odd–Even turn model. However, non-minimal paths are not guaranteed to exist”. Such observations reflect the realization that, while not impossible, developing turn-model based non-minimal routing algorithms is a non-trivial endeavor.
However, as pointed out by Glass and Ni [5], “Non-minimal routing, however, is more adaptive and fault tolerant”. Inherently, non-minimal routing paths provide greater flexibility in avoiding local routing hot spots or searching for detours when encountering a defective channel. Hence, it is beneficial to develop non-minimal routing algorithms under the turn-model constraints.
In this paper, three novel non-minimal routing algorithms based on the Odd–Even [6], West-First, and Negative-First [5] turn models are proposed. In particular, new heuristic routing rules are developed to permit the exploration of non-minimal routing paths without violating the turn-prohibition rules of the corresponding turn model. It is shown that the proposed non-minimal routing algorithms are deadlock free, livelock free, and backward compatible with existing minimal routing schemes. It is shown experimentally that the proposed non-minimal routing algorithms promise significant performance improvement compared to existing minimal routing schemes for certain on-chip data traffic patterns.
The remainder of this paper is organized as follows. Section 2 presents the background on the NoC routing problem and describes the challenges involved in developing non-minimal routing algorithms under turn-model constraints. Section 3 introduces the proposed turn-model based non-minimal routing algorithms. Section 4 presents the performance evaluation results. Finally, Section 5 provides some brief concluding remarks.
Section snippets
Background
In this section, fundamental characteristics of NoC routing schemes including existing turn-model based non-minimal routing algorithms will be reviewed, and the advantages and disadvantages of non-minimal routing approaches will be discussed.
Design methodologies
In this section, details of the proposed design methodologies are discussed. These methodologies include the definition of a direction-aware path selection mechanism; a description of the proposed turn-model based non-minimal routing algorithms; a formal proof of the deadlock free, livelock free, and minimal routing compatibility of the three schemes; and finally, a comparison of the routing adaptivity of the three algorithms with that of existing schemes.
Experimental results
In this section, the performance and implementation cost of the proposed Non-Minimal Routing (NMinR) algorithms are compared against those of the Minimal Routing (MinR) schemes.
Discussion and conclusion
In this study, the performance and cost of the proposed non-minimal routing algorithms have been analyzed with a buffer size configuration referring to the TeraFLOPS Processor (Intel 80-core) [29]. Although the area of a router design is dominated by the buffer space (as in the implementation of [33]), the router buffers occupy only a small fraction of the system-wide SRAM memory in most architectures (e.g., CMPs with multi-megabyte caches) [27]. Therefore, future design efforts should
Acknowledgement
This work was partially supported by the National Science Council, under Grants 99-2220-E-002-041 and 100-2220-E-002-012.
Wen-Chung Tsai received the B.S. degree in Computer Science and Information Engineering from Tamkang University in 1996. He received the M.S. degree in Electrical Engineering from National Cheng Kung University in 1998. He received the Ph.D. degree in Electronics Engineering from National Taiwan University in 2011. He is currently a researcher of Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan. His research interests include
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Wen-Chung Tsai received the B.S. degree in Computer Science and Information Engineering from Tamkang University in 1996. He received the M.S. degree in Electrical Engineering from National Cheng Kung University in 1998. He received the Ph.D. degree in Electronics Engineering from National Taiwan University in 2011. He is currently a researcher of Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan. His research interests include system-on-chip, network-on-chip, computer network, and mobile telecom.
Kuo-Chih Chu received the B.S. degree in Information Engineering and Computer Science from Feng-Chia University, Taichung, Taiwan, R.O.C., in 1996 and received M.S. and Ph.D. degrees in Electrical Engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1998 and 2005, respectively. He is currently an Associate Professor with the Department of Electronic Engineering, Lunghwa University of Science and Technology, Taoyuan, Taiwan, R.O.C.
Yu-Hen Hu received the B.S.E.E. degree from the National Taiwan University, Taipei, Taiwan, R.O.C., in 1976, and the M.S.E.E. and Ph.D. degrees from the University of Southern California, Los Angeles, in 1980, and 1982, respectively. From 1983 to 1987, he was an Assistant Professor with the Electrical Engineering Department, Southern Methodist University, Dallas, TX. Since 1987, he has been in the Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, where he is currently a Professor. He has served as an Associate Editor for the European Journal of Applied Signal Processing and Journal of VLSI Signal Processing. He has broad research interests ranging from design and implementation of signal processing algorithms, computer-aided design and physical design of VLSI, pattern classification and machine learning algorithms, and image and signal processing in general. He has published more than 200 technical papers and edited several books in these areas. Dr. Hu has served as an Associate Editor for the IEEE Transactions of Acoustic, Speech, and Signal Processing, IEEE Signal Processing Letters, and IEEE Multimedia Magazine. He has served as the Secretary and an executive committee member of the IEEE Signal Processing Society, a board of governors of the IEEE Neural Network Council representing the Signal Processing Society, the Chair of the Signal Processing Society Neural Network for Signal Processing Technical Committee, and the Chair of the IEEE Signal Processing Society Multimedia Signal Processing Technical Committee (2004–2005). He is also a steering committee member of the International Conference of Multimedia and Expo, IEEE Transactions on Multimedia on behalf of the IEEE Signal Processing Society. Professor Hu is a fellow of IEEE.
Sao-Jie Chen received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, ROC, in 1977 and 1982 respectively, and the Ph.D. degree in electrical engineering from Southern Methodist University, Dallas, USA, in 1988. Since 1982, he has been a member of the faculty in the Department of Electrical Engineering, National Taiwan University, where he is currently a full professor. During the fall of 1999, he was a visiting professor in the Department of Computer Science and Engineering, University of California, San Diego, USA. During the fall of 2003, he held an academic visitor position in the Department of System Level Design, IBM Thomas J. Watson Research Center, Yorktown Heights, New York, USA. He obtained the “Outstanding Electrical Engineering Processor Award” by the Chinese Institute of Electrical Engineering in December 2003 to recognize his excellent contributions to EE education. During the falls of 2004–2009, he was a visiting professor in the Department of Electrical and Computer Engineering, University of Wisconsin, Madison, USA. His current research interests include: VLSI physical design, SOC hardware/software codesign, and Wireless LAN and Bluetooth IC design. Dr. Chen is a member of the Chinese Institute of Engineers, the Chinese Institute of Electrical Engineering, the Institute of Taiwanese IC Design, the Association for Computing Machinery, and a senior member of the IEEE Circuits and Systems and IEEE Computer Societies.