VLSI architecture for parallel radix-4 CORDIC

Abstract

COordinate Rotation DIgital Computer (CORDIC) algorithm is an iterative method for fast hardware implementation of the elementary functions such as trigonometric, inverse trigonometric, logarithm, exponential, multiplication and division functions in a simple and elegant way. This paper presents a regular and scalable VLSI architecture for the implementation of parallel radix-4 rotational CORDIC algorithm. Thorough comparison of the proposed architecture with the available architectures has been carried out to show the latency and the hardware improvement. Furthermore, the proposed architecture is coded for 16-bit precision using the VHDL language. The functionally simulated net list has been synthesized with 90 nm CMOS technology library and the area-time measures are provided. This architecture is also implemented using Xilinx ISE7.1i software and a Virtex device.

Introduction

The advances in the VLSI technology have stimulated a great interest in developing special purpose parallel processor arrays to facilitate realtime signal processing. The basic arithmetic operations required in VLSI arrays are implemented with multiplication and accumulation (MAC) unit. The reduction in the hardware cost also motivated the development of sophisticated Digital Signal Processing (DSP) algorithms to enhance the performance of modern DSP systems. Many of these sophisticated algorithms require the evaluation of elementary functions such as trigonometric, exponential and logarithmic functions. The commonly used software solutions for the digital implementation of these functions are table lookup method and polynomial expansions. These methods are preferred for applications requiring low resolution. For higher precision, table look up method is not feasible and polynomial approximation methods involve computationally intensive multiplications and additions/subtractions. These functions cannot be evaluated with MAC based arithmetic units since they result in significant performance degradation. The COordinate Rotation DIgital Computer (CORDIC) algorithm is developed [1] as an alternative solution for the computation of these elementary functions. CORDIC offers an unified iterative solution to efficiently evaluate each of these elementary functions by formulating all evaluation tasks as a rotations of 2 × 1 vector in various coordinate systems. The same CORDIC processor can evaluate all these elementary functions using the same hardware within the same time by varying a few simple parameters.

In the conventional CORDIC [1], rotation of a two dimensional vector by a target angle is achieved by decomposing the desired rotation angle into the weighted sum of a set of predefined elementary rotation angles such that the rotation through each of them can be realized with simple shift-and-add operations. Subsequently, the CORDIC algorithm is extended [2] to propose a unified algorithm for computation of the rotation in circular, linear, and hyperbolic coordinate systems, embedding coordinate systems as a parameter. These transcendental functions are the core for many applications such as digital signal processing [3], image processing [4], [5], and kinematic processing [6]. In [4], FPGA realization of a 16-bit CORDIC based 128 point FFT processor for biomedical signal processing is presented. The choice of the CORDIC algorithm for realizing the basic butterfly operation for the FFT saves hardware compared to its counterparts employing other techniques. The advances in the VLSI technology have extended the application of CORDIC algorithm recently to the field of biomedical signal processing [7], [8], neural networks [9], and wireless communications [10], [11] to mention a few. In [8], CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis is presented which requires less hardware in contrast to the ROM based implementations of windowing functions. In [10], digit-pipelined Direct Digital Frequency Synthesis (DDFS) based on Differential CORDIC is presented which does not incur the exponential growth of hardware with precision in contrast to the ROM lookup table approach of realization of DDFS, where all the required sine/cosine values are stored in a ROM.

The design of an architecture for the implementation of CORDIC algorithm with an iterative nature depends on the design constraints such as silicon area, speed and power consumption. In general, the architectures can be broadly classified as folded and unfolded. Folding provides a means for trading area for time in signal processing architectures. Folded architectures are obtained by time multiplexing all the iterations on a single functional unit. These folded architectures can be further subdivided into bit-serial and word-serial architectures depending on whether the functional unit implements the logic for one bit or one word of each iteration of the CORDIC algorithm. The CORDIC algorithm has traditionally been implemented using a bit serial architecture [1] and a word serial architecture [2], [12]. The major drawback of these architectures is high latency. This is overcome by unfolding the iteration process, so that each of the processing elements always perform the same iteration. The unfolded architecture realizes the shift operation using hardwired shifts rather than time and area consuming barrel shifters and eliminates the ROM required for storing the elementary angles. The latency can be further decreased by employing redundant arithmetic in the implementation of CORDIC algorithm.

A redundant radix-2 CORDIC is proposed using carry save (CS) arithmetic [13] to reduce the time for each iteration of the conventional CORDIC. However, it results in variable scale factor. In order to reduce the cost of this redundant CORDIC for the scale factor calculation and the scaling operation, two constant scale factor redundant CORDIC algorithms are proposed using signed digit (SD) arithmetic [14]. Since these methods lead to more complicated iterations or extra correcting rotations, two methods using CS arithmetic [15], [16] and two methods using SD arithmetic [16], [17] are proposed to reduce latency. These methods offer low latency solutions at the cost of increasing hardware. The latency as well as the hardware can be reduced by employing higher radix schemes [18], [19]. Both redundant and higher radix based CORDIC algorithms are still iterative in nature, and greatly restrict the speed of implementation of the algorithm. This prompted the researchers to devise methods for reducing the delay of iteration.

The delay of each iteration is composed of two delays, the delay to predict the new rotation direction and the delay involved in the computation of rotation. The total computation delay can be reduced by precomputing the direction of microrotations [20], [21]. It can be further reduced by eliminating iterative nature in the x/y path completely [22] or partially [23]. Based on the study of the available architectures and algorithms [24], we observe that the latency and hardware of radix-2 CORDIC can be reduced by employing redundant radix-4 arithmetic and parallelizing the determination of direction of rotations [25]. In this paper, we present the design of an unfolded architecture to reduce the computation delay of CORDIC.

The remainder of the paper is organized as follows. We present a brief review of a rotational radix-4 CORDIC algorithm in Section 2. The proposed architecture is discussed in Section 3. The latency and hardware complexity comparison of the proposed architecture with the unfolded parallel architectures available in the literature is presented along with the synthesis results in Section 4. Finally, conclusions are presented in Section 5.