Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model

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Abstract

In deeply scaled CMOS technologies, Bias Temperature Instability (BTI) is one of the most critical degradation mechanisms impacting the device reliability. This study presents the BTI evaluation of gates covering both the PMOS and NMOS degradation in a workload dependent, atomistic trap-based, stochastic BTI model. The gate propagation delay depends on the gate intrinsic delay, the input signal characteristics, and the output load. In this paper, the impact of (1) duty factor, (2) periodic clock-based and non-periodic random input sequences, (3) gate, and (4) drive strength to the BTI degradation are investigated. Statistical studies show a mean degradation of 3% and a worst-case of 27%. Moreover, the near-critical paths with lower drive strength cells are 3.7× more susceptible to BTI degradation than the critical paths with higher drive strength cells. Next, the relative degradations of the propagation delays for the well-known gates (i.e. INV, NAND, NOR, AOI) are presented. Under the same stress stimuli, degradations of the gate propagation delays differ by 4.5×.

Introduction

In the Deep Submicron (DSM) era aggressive and asymmetric scaling below the 45  32 nm nodes have multiplied the electric field levels in field effect devices rather than scaled them [1]. Moreover, due to such small dimensions even the reduced number of defects in these devices results in a dramatic increase in the time-dependent variability [2]. Reliability issues, e.g. negative/positive bias temperature instability (NBTI/PBTI), hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB both for the device and interconnect) are more dominant and appreciable than ever before as the near-term challenges [3]. The continuity of the CMOS scaling is threatened in terms of the reliable computing, acceptable device lifetime, device performance, etc. [4], e.g., for BTI, Reaction–Diffusion (R–D) model based studies present 8–10% degradation on the ISCAS benchmark circuits after 1–5 years usage [5], [6]. Additionally, the workload dependence of degradation is shown by the Atomistic trap-based model [7].

Aging issues are not constant static problems, instead they are heavily workload dependent [5], [8]. In case of BTI the physical nature of trapping leads to deterioration and recovery phases [9]. The recovery phase proceeds approximately logarithmically, i.e. it quickly anneals at the beginning, and then slows down. Even a short recovery phase may anneal up to 75% of the previous degradation [10]. R–D model based studies generalize the degradation under DC/AC stress by polynomially fitting the threshold voltage shift (ΔVth) onto the trend lines [5], [11], [12], [13]. However, the real workload dependency is oversimplified, since the trap history of each input stimulus is unique in its nature [7], [8], [14]. BTI is a time-dependent degradation mechanism where the number of traps that are occupied/released and the corresponding ΔVth per each trap dynamically evolve during the device lifetime [15], [16]. This postulates itself as the requirement for the workload dependent, dynamic parameter based reliability modeling [7].

Compared to the state-of-the-art, this study applies a stochastic, workload dependent, atomistic trap-based BTI model. The model parameters are statistically initialized at the beginning, and deterministically updated on the run-time. Secondly, both the NBTI and PBTI are focused on, whereas the previous studies were focusing on NBTI-only, and ignoring PBTI [5], [6], [11], [12], [13]. The rise propagation delay that is dominated by the pull-up PMOS network is also correlated with the performance of the pull-down NMOS network, and vice versa. Hence, the BTI impact on PMOS and NMOS is analyzed together with the fall and rise propagation delays. Moreover, the impact of the duty factor (DF), the periodic clock-based vs. non-periodic arbitrary stimuli with a given DF, the gate and drive strength are experimented through the Monte-Carlo simulations, which provides a more realistic and complete analysis than the previous BTI studies. In addition, the degradation of the critical vs. non-critical paths, and the gate propagation delays are comparatively analyzed in detail. The resulting trends can be easily generalized and applied to the pull-up and pull-down network based CMOS logic gates of the complete datapath stages. Thus, this study is unique by combining these experiments and generalizable trends with a stochastic, workload dependent, atomistic trap-based BTI model that covers both the NBTI and PBTI, and by performing each experiment as a Monte-Carlo simulation.

The rest of the paper is organized as follows. Section 2 motivates the reasons behind this study through an example circuit. Section 3 provides the notable state-of-the-art in BTI modeling. Section 4 explains the applied BTI model at a high level. Section 5 shows the experimental setup. Section 6 presents and discusses the results. Finally, the last section summarizes our findings.

Section snippets

Motivational example

A typical design consists of a critical path (e.g. P2) and many near-critical paths (e.g. P1, P3), which have timing slacks close to the critical path’s as visualized in Fig. 1. Timing paths start at a flip–flop (FF), propagate through various combinational gates (C) and wires (W), and end at a flip–flop. The timing of a path is the sum of each component’s delay on the path (e.g. C1 + W1 + C2 + W2, etc.). Since BTI is a device reliability issue, this study limits itself only to the gate delay

State-of-the-art

Previous studies are discussed in the order of a bottom-up hierarchy, starting from the device level, and going up to the circuit level BTI degradation modeling.

Background of atomistic trap-based BTI model

This model is based on the capture and emission of single traps in the stress/relaxation phases of NBTI/PBTI with time constants. To model these physical mechanisms, six parameters are inserted to a device:

  • 1.

    Ntraps the number of traps in the device gate-oxide layer. It is generated by a Poisson distribution proportional to the area (W, L) and the device trap density (Dtraps).

  • 2.

    τc,e the time constants for the capture and emission of a single trap. Due to the voltage dependency, there are two types of

Experimental setup

The BTI annotation script orthogonally inserts the Ntraps, τc,e, and ΔVth from the statistical distributions. Each time when the same netlist is run through the flow, the resulting non-degraded BTI enhanced netlist has different initial values. Therefore, Monte-Carlo simulations are performed with the same array of 1000 seeds for each experiment to generate multiple BTI enhanced netlists.

Results and discussion

The distributions of the rise/fall propagation delays before-, and after-degradation are generated as in Fig. 2. The mean, variance and the maximum values for each distribution are calculated. The degradation percentages are graphed as follows:

  • 1.

    Mean degradation is the difference between the means of the before-, and after-degradation distributions. It indicates how the distribution mean shifts due to the occupied traps.

  • 2.

    Worst degradation is the difference between the mean of the before-, and the

Conclusion

In this work, gate BTI degradation is evaluated with a workload dependent, atomistic trap-based BTI model. The impact of the duty factor, periodic vs non-periodic stimuli, the gate and drive strength are assessed. Opposite behavior of the rise/fall time degradations are shown. Duty factor is an indicator for the mean degradation, but not for the worst degradation. Moreover, the higher susceptibility of the near-critical paths to the BTI is shown. Relative degradation of gates and propagation

Acknowledgment

This work is partly supported by Agency for Innovation by Science and Technology in Flanders (IWT).

Halil Kükner received his B.Sc. degree from Sabancı University, Istanbul, Turkey, in 2008; and his M.Sc. degree from Technische Universiteit Delft, Netherlands, in 2010; both in Electrical Engineering. Currently he is a Ph.D. researcher in the Circuits and Systems for ICT group at imec, Leuven, Belgium, and also at the Department of Electrical Engineering of Katholieke Universiteit Leuven, Belgium. He has the Best Paper Award at DTIS. His research interests include microarchitecture, image and

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      Particularly for very small area devices in modern technologies, BTI variability may significantly impact circuit life time, as shown by [9], whereas low-frequency noise variability may easily span five orders of magnitude [10,11]. Therefore, understanding the trapping phenomenon and accurately modeling it is essential for the development of more reliable circuits; in this regard, many efforts were made in order to model and simulate BTI and RTS, in the works of [12–16]. This paper provides a critical discussion on the unified description for RTS and BTI phenomena, emphasizing on the assumptions required for adequately describing the dependences on operating conditions observed in literature.

    Halil Kükner received his B.Sc. degree from Sabancı University, Istanbul, Turkey, in 2008; and his M.Sc. degree from Technische Universiteit Delft, Netherlands, in 2010; both in Electrical Engineering. Currently he is a Ph.D. researcher in the Circuits and Systems for ICT group at imec, Leuven, Belgium, and also at the Department of Electrical Engineering of Katholieke Universiteit Leuven, Belgium. He has the Best Paper Award at DTIS. His research interests include microarchitecture, image and video processing, motion estimation, memory built-in self-testing, and digital circuit reliability.

    Pieter Weckx received his M.Sc. degree in Nanoscience and Nanotechnology from the Katholieke Universiteit Leuven, Belgium, in 2011, where he is currently working towards the Ph.D. degree in electronics and electrical engineering. His research interests are focused on the modeling and simulation of time-dependent variability problems in nanoscaled electronic devices, statistical circuit simulations and stochastic/deterministic clustering of circuit degradation behavior.

    Praveen Raghavan obtained his Ph.D. from KULeuven in 2009. He received his Masters in Electrical Engineering from Arizona State University, Tempe, USA. He received his Bachelors Degree in Electrical Engineering from Regional Engineering College Trichy, India. In 2007, he was also a visiting researcher at Berkeley Wireless Research Center (BWRC), University of Berkeley, California.

    He is currently a principal scientist in the circuits and systems for ICT group at imec, where he is the lead processor architect for IMEC’s next generation 4G software defined radio platform. His research interests include processor architecture design, impact of deeply scaled technology on architectures/systems, reliability, variability, low power design, and software defined radios. He has published over 80 conference and journal papers in this area and holds more than 30 patents.

    Ben Kaczer is a Principal Scientist at imec, Belgium. He received the M.S. degree in Physical Electronics from Charles University, Prague, Czech Republic, in 1992 and the M.S. and Ph.D. degrees in Physics from The Ohio State University, Columbus, in 1996 and 1998, respectively. In 1998 he joined the reliability group of imec, Leuven, Belgium, where his activities have included the research of the degradation phenomena and reliability assessment of SiO2, SiON, high-k, and ferroelectric films, planar and multiple-gate FETs, circuits, and characterization of Ge/III–V and MIM devices. He is currently serving on the IEEE T. Electron Dev. Editorial Board.

    Francky Catthoor received a Ph.D. in EE from the Katholieke Univ. Leuven, Belgium in 1987. Between 1987 and 2000, he has headed several research domains in the area of high-level and system synthesis techniques and architectural methodologies, including related application and deep submicron technology aspects, all at IMEC Leuven, Belgium. Currently he is an IMEC fellow. He is also part-time full professor at the EE department of the K.U.Leuven.

    He has been associate editor for several IEEE and ACM journals, like Trans. on VLSI Signal Procsesing, Trans. on Multi-media, and ACM TODAES. He was the program chair of several conferences including ISSS’97 and SIPS’01. He has been elected IEEE fellow in 2005.

    Liesbet Van der Perre received the M.Sc. degree in Electrical Engineering from the K.U.Leuven, Belgium, in 1992, involving thesis work at the Ecole Nationale Superieure de Telecommunications in Paris. She graduated summa cum laude with a PhD in electrical engineering from the K.U.Leuven in 1997.

    Liesbet joined IMEC in 1997, where she engaged in pioneering designs for wireless communications. Currently, she is director of imec’s wireless programs comprising reconfigurable radios and mm-wave solutions. L. Van der Perre is also a professor at the K.U.Leuven, Belgium since 2008. She’s an author and co-author of over 250 publications.

    Rudy Lauwereins is vice president of imec, which performs world-leading research and delivers industry-relevant technology solutions through global partnerships in nano-electronics, ICT, healthcare and energy. He is director of imec’s Smart Systems Technology Office, guiding the strategic research decisions in energy efficient green radios, vision systems, (bio) medical and lifestyle electronics, wireless autonomous transducer systems, large area organic electronics, photovoltaic systems, battery systems, and More than Moore technologies. He is also a part-time Full Professor at the Katholieke Universiteit Leuven, Belgium, where he teaches Computer Architectures in the Master of Science in Elektrotechnical Engineering program.

    Before joining imec in 2001, he held a tenure Professorship in the Faculty of Engineering at the Katholieke Universiteit Leuven since 1993. He had obtained a Ph.D. in Electrical Engineering in 1989. Professor Lauwereins has authored and co-authored more than 380 publications in international journals, books and conference proceedings. He is a fellow of the IEEE.

    Guido Groeseneken received the M.Sc. degree in electrical and mechanical engineering and the Ph.D. degree in applied sciences from the Katholieke Universiteit Leuven (K.U. Leuven), Leuven, Belgium, in 1980 and 1986, respectively.

    In 1987, he joined the R& D Laboratory, Interuniversity Microelectronics Center (IMEC), Leuven, where he is currently responsible for the research in reliability physics for deep-submicrometer CMOS technologies. From October 2005 to April 2007, he was also responsible for the IMEC post-CMOS nanotechnology program within IMECs core partner research program. Since 2001, he has also been a Professor with the ESAT Department, K.U. Leuven, where he is the Program Director of the Master in nanoscience and nanotechnology, and is also coordinating a European Erasmus Mundus Master program in nanoscience and nanotechnology. He has made contributions to the fields of nonvolatile semiconductor memory devices and technology, reliability physics of VLSI technology, hot-carrier effects in MOSFETs, TDDB of oxides, negative-bias-temperature instability effects, ESD protection and testing, plasma-processing-induced damage, electrical characterization of semiconductors, and characterization and reliability of high-k dielectrics. Recently, he has also interest in nanotechnology for post-CMOS applications, such as carbon nanotubes for interconnect applications, and tunnel FETs for alternative nanowire devices.

    Prof. Groeseneken has served as a technical program committee member of several international scientific conferences, among which the IEEE International Electron Devices Meeting (IEDM), the European Solid State Device Research Conference, the International Reliability Physics Symposium, the IEEE Semiconductor Interface Specialists Conference, and the EOS/ESD Symposium. From 2000 to 2002, he also acted as the European Arrangement Chair of IEDM. In 2005, he was the General Chair of the Insulating Films on Semiconductor conference, organized in Leuven. He has authored or coauthored more than 500 publications in international scientific journals and in international conference proceedings, six book chapters, and ten patents in his fields of expertise. He became an IMEC Fellow in 2007.

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