Multiple detection test generation with diversified fault partitioning paths

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Abstract

The dependability of current and future nanoscale technologies highly depends on the ability of the testing process to detect emerging defects that cannot be modeled traditionally. Generating test sets that detect each fault more than one times has been shown to increase the effectiveness of a test set to detect non-modeled faults, either static or dynamic. Traditional n-detect test sets guarantee to detect a modeled fault with minimum n different tests. Recent techniques examine how to quantify and maximize the difference between the various tests for a fault. The proposed methodology introduces a new systematic test generation algorithm for multiple-detect (including n-detect) test sets that increases the diversity of the fault propagation paths excited by the various tests per fault. A novel algorithm tries to identify different propagating paths (if such a path exists) for each one of the multiple (n) detections of the same fault. The proposed method can be applied to any linear, to the circuit size, static or dynamic fault model for multiple fault detections, such as the stuck-at or transition delay fault models, and avoids any path or path segment enumeration. Experimental results show the effectiveness of the approach in increasing the number of fault propagating paths when compared to traditional n-detect test sets.

Introduction

Modern digital systems depending on reliable nanoscale integrated circuits play a critical role to the consistency of the digital era evolution. Applications varying from popular consumer electronics products such as smartphones to highly dependable aviation systems feature different configurations with different dependability needs. In addition, technology shrinking highly affects the testability of nanoscale components due to the existence of emerging defects that cannot be modeled efficiently. Moreover, process variability for heterogeneous architectures can increase the diversity of these defects and make the already challenging process of developing effective tests even more complicated. Thus, the selected test methodology becomes the critical factor for obtaining high manufacturing yield and at the same time ensuring the dependability and the reliability of the final system.

In order to cope with this demanding trend, more sophisticated post-manufacturing testing methodologies and/or procedures are introduced. A straightforward, yet hard, approach, is to develop improved fault models of increased complexity in an attempt to emulate the behavior of real defects at different levels of abstraction. However, the diversity of the possible defects limits this approach to applications for specific problems for which a large number of assumptions hold. Moreover, test engineers rarely have access to detailed layout information before the fabrication phase and, hence, they cannot incorporate the actual defects profile in the test generation process. For this reason, an alternative approach employs multiple detections per modeled fault, using well established fault models of linear complexity like the stuck-at and transition fault models, in an attempt to catch manufacturing defects that cannot be detected by single detect test sets.

This alternative approach relies on the speculation that detecting a fault more than one time, by generating a number of different tests for each modeled fault, contributes in achieving higher defect coverage. Indeed, previous works on test generation considering each fault multiple times have shown to give high non-modeled fault coverage and, thus, higher test quality [1], [2], [3], [4], [5], [6], [7], [8]. The vast majority of the ATPG methods for multiple-detect (or n-detect) test sets mainly concentrate on reducing the test generation effort and, at the same time retain a small test set size. Moreover, it is important to consider the diversity between the different tests per fault in order to achieve the desired quality. Sets with diverse tests per targeted modeled fault have been shown to achieve higher defect and non-modeled fault coverage [9], [10], [11], [12], [13]. Diversity, i.e., how different are the tests that detect a fault, has been defined in various manners. [13] proposed a definition for sufficiently different tests, in terms of how different certain primary input signal values are with respect to the already generated tests for a fault. The works in [9], [10], [13] introduce measures that quantify the difference between tests detecting the same fault, either based on the internal signal values that excite the fault [9], [13] or propagate the fault to a primary output [10]. In essence, the motivation behind the approach followed by all these methods is to introduce sufficient randomness to input signal values when distinguishing the tests. For this purpose, primary inputs can be classified in two groups: (a) those affecting the targeted fault (either activate the fault or propagate the fault to some primary output) and (b) those which do not affect the targeted fault. The traditional definition of n-detect does not distinguish these two groups and, thus, a single different bit value in either group can give a different test to be considered for the same fault. Still, when higher defect coverage is desired, different values for the inputs in the first group (affecting the modeled fault) give tests that activate the targeted fault with different internal signal values and/or propagate the fault effect to some primary output via different propagation paths. In this direction, the work in [11], [12] considers the physical neighborhood of the fault site and enforces that the different tests assign specific values on the neighboring signal lines. Such techniques, however, result in test sets with larger size than the traditional n-detect test sets because the constraint to have n different values in the fault site neighborhood prevent test set compaction from merging the obtained tests to reduce the set size.

From the existing methods that generate diverse tests, [8], [14] attempt to incorporate information on activation and/or propagation paths for the different tests by propagating the fault effect to different outputs. The work in [8] attempts to propagate all transition faults to all the different outputs while the approach of [14] selects from a large n-detect pattern repository tests based on an output deviation statistical metric. None of the existing techniques attempts to explicitly identify or even estimate the number of the different activation/propagation paths for each fault. Especially, when delay fault models are considered, targeting different activation/propagation paths for the different tests that target a fault is of even higher importance, since they can have a large impact on the final test set quality regarding the detection of dynamic defects [15], [16]. Dynamic defects such as small delay defects [16], [17] may escape detection if the test generation process considers fault models that concentrate of line focalised defects (e.g. stuck-at, bridging and transition faults). Hence, having tests that activate and/or propagate each targeted fault through different paths can be beneficial for detecting distributed delays along physical paths of the circuit, without explicitly considering path delay faults [18] which are known to be of exponential complexity.

This work proposes a methodology for generating test sets that target each modeled fault multiple times such that each one of the different tests detecting a fault attempts to propagate the fault via a different propagating path than the remaining tests. The number of different tests per fault can be fixed (in which case the obtained test set can be classified as an n-detect test set), or it can vary among the various faults (i.e., n1 for fault f1,n2 for fault f2, etc.). For a single fault fi where only k<ni such test exists (the proposed method can efficiently determine this) two different approaches are examined: (a) generate only k different tests for that fault, each propagating the fault through a different path and, (b) ni tests are still generated, however, two or more tests that propagate a fault through the same propagating path can still differ on the primary input values that do not affect propagation. In essence, the proposed method can work complementary to the methods of [9], [11], [12], [13] to generate tests with different excitation conditions or sufficiently different test pattern values. The approaches in (a) and (b) can be combined, if desired, to give test sets that meet predefined size bounds by exploring the full range of detections between k and ni . Hence, the proposed methodology can generate n-detect test sets (when n1=n2==ni=n) or multiple-detect test sets where the number of tests per fault is determined based on the number of its possible propagating paths and the desired test set size.

The proposed method gives a systematic way of partitioning the circuit under test into subcircuits with limited path overlap. For each fault a number of such subcircuits are obtained each of which contains a number of paths that may allow the propagation of the fault to at least one primary output. Each subcircuit is constructed in order to contain potentially propagating paths that are as different as possible from the paths in the other subcircuit for the same fault. The proposed partitioning algorithm performs a breadth-first traversal on a fault cone (part of the circuit starting from a fault site ending at the primary outputs) and groups the potentially propagating paths (paths segments) in subcircuits, by examining the cone’s fanout branches. In this process no path or path segment is ever enumerated. For each fault fi,ni different subcircuits are obtained, where ni can be defined based on the number of propagating paths existing for the fault. Next, test generation is performed for each different subcircuit per fault. In this manner, the generated tests for some fault tend to propagate the fault effect via different paths. Actually, the propagating paths are highly different since two paths in different subcircuits have minimum line overlap. In order to control the test set size, the proposed test generation problem is reduced to a graph-theoretical problem where the graph vertices represent the different fault detections and the concept of fault compatibility is used in order to merge different vertices to compact the generated test set.

While the proposed methodology is presented in this context for the stuck-at fault model, it can be generalized to any fault model that is linear to the size of the circuit. For instance, the transition fault model can be used in the same manner. Specifically, for the transition fault model, subcircuit partitioning can be applied to the activating cone (in addition of the propagating cone), in order to further diversify the ni different tests for fault fi.

The main contributions of the proposed method are:

  • i.

    In contrast to existing methods, test generation is performed considering propagation conditions via different paths.

  • ii.

    Small overlap between different propagating paths is also considered.

  • iii.

    Path and path segment enumeration is explicitly avoided, allowing the method to be efficient and scalable.

  • iv.

    It can be used complementary to other methods that generate diverse multiple detect test sets. For example, the methods of [9], [11], [13] can be used on-top of the proposed method. Hence, each of the generated test will propagate the fault via a different propagating path and with different (specific if necessary, as in the case of [11]) internal signal values than any of the other tests that detect the same fault.

  • v.

    The method can be easily generalized to apply to any fault model (other than the stuck-at fault model) that is linear to the size of the circuit. In particular, for dynamic models such as the transition delay fault model, the method may consider different activation paths on top of the different propagating paths. Using path-related information to enhance the traditional transition delay fault model has been shown to increase the ability of the test set to detect additional, non-explicitly modeled, defects [15].

The rest of the paper is organized as follows. Section 2 gives definitions and necessary notation. Section 3 describes a systematic, and linear to the circuit size, method for partitioning a circuit under test into different subcircuits per fault in such a way that their overlap is small. Section 4 presents a new dynamic ATPG procedure for multiple detection test sets that generates a set of tests to detect each fault multiple times, such that the fault propagates via at least one propagating path in every different subcircuit. Section 5 presents and discusses the obtained experimental results which demonstrate the effectiveness of the proposed methodology in terms of increasing the number of different fault propagating paths. Furthermore, the applicability of the path diversified test sets in recent test ranking/selection methods for better defect coverage is demonstrated. Section 6 concludes the paper.

Section snippets

Preliminary notation and definitions

In this section we give necessary notation and definitions used throughout this paper. A relevant discussion after each definition shows how they are used in the proposed methodology (explained in detail in Section 3).

The proposed methodology starts with a static partitioning of the circuit under test into groups of different paths. These groups of paths are next used by the test generation procedure, in order to increase the diversity of the different tests (detections) that target a specific

Partitioning the fault site cone into propagation subcircuits

The proposed methodology focuses on propagation diversity between the different tests targeting the same fault. In order to achieve high diversity we perform test generation considering the different propagation subcircuits for each fault. This way we enforce implicit partitioning of the test space for each fault based on a fault propagation criterion. Important role in the proposed methodology plays the partitioning process.

According to Definition 1 each fault defines a cone which starts at

Multiple detect test generation

The generation of multiple test functions per fault described in the previous section serves as a good starting point for obtaining a multiple test set that has multiple detections for each considered fault, each of which targets different propagation conditions in the circuit under test. In this section we describe how the proposed methodology generates the propagating path diverse tests. The process (shown in Algorithm 3) is a graph based approach that performs conditional merging of tests

Experimental results

The proposed methodology was implemented using ANSI C++, in a UNIX environment. All experiments were run on a 1 GHz SunBlade 1500 with 4 GB of RAM, using the ISCAS’85 and the full-scan versions of the ISCAS’89 benchmarks. The function-based ATPG tool was implemented using Binary Decisions Diagrams (BDDs) (on top of the CUDD package [22]). The collapsed fault list for the single stuck-at fault model was derived using the Checkpoint Theorem.

Conclusions

This work presents a test pattern generation method which attempts to increase the number of distinct paths in the circuit that propagate a fault to a primary output, for multiple-detect test sets. A new linear method for obtaining subcircuits per fault cone and enforcing fault propagation through each subcircuit is presented. A graph-based algorithm controls the size of the test set and preserves a given number of detections per fault, not necessarily equal for all the faults considered. The

Acknowledgments

This work has been partially supported by the Cyprus Research Promotion Foundation.

Stelios N. Neophytou received the Engineering Diploma from the Computer Engineering and Informatics Department of University of Patras, Patras, Greece, and the Ph.D. degree from the Department of Electrical and Computer Engineering, University of Cyprus, Nicosia, Cyprus, in 2003 and 2009, respectively. Currently, he is a Assistant Professor with the Electrical and Computer Engineering Department, University of Nicosia, Cyprus. His research concentrates on the area of electronic design and

References (25)

  • B. Benware, C. Schuermyer, S. Ranganathan, R. Madge, P. Krishnamurthy, N. Tamarapalli, K.-H. Tsai, J. Rajski, Impact of...
  • J. Geuzebroek, E.J. Marinissen, A. Majhi, A. Glowatz, F. Hapke, Embedded multi-detect ATPG and its effect on the...
  • K. Kantipudi, V. Agrawal, A reduced complexity algorithm for minimizing n-detect tests, in: Proc. of VLSI Design, 2007,...
  • S. Lee, B. Cobb, J. Dworak, M.R. Grimaila, M.R. Mercer, A new ATPG algorithm to limit test set size and achieve...
  • E.J. McCluskey, C.-W. Tseng, Stuck-fault tests vs. actual defects, in: Proc. of ITC, 2000, pp....
  • S.N. Neophytou, M.K. Michael, On the relaxation of n-detect test sets, in: Proc. of VTS, 2008, pp....
  • I. Pomeranz et al.

    Forming N-detection test sets without test generation

    ACM Trans. Des. Autom. Electr. Syst.

    (2007)
  • C.-W. Tseng, E.J. McCluskey, Multiple-output propagation transition fault test, in: Proc. of ITC, 2001, pp....
  • J. Dworak, B. Cobb, J. Wingfield, M.R. Mercer, Balanced excitation and its effect on the fortuitous detection of...
  • M. Grimaila, S. Lee, J. Dworak, K. Butler, B. Stewart, H. Balachandran, B. Houchins, V. Mathur, J. Park, L.-C. Wang, M....
  • Y.-T. Lin et al.

    Physically-aware N-detect test

    IEEE Trans. CAD

    (2012)
  • J. Nelson, J. Brown, R. Desineni, R. Blanton, Multiple-detect ATPG based on physical neighborhoods, in: Proc. of DAC,...
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    Stelios N. Neophytou received the Engineering Diploma from the Computer Engineering and Informatics Department of University of Patras, Patras, Greece, and the Ph.D. degree from the Department of Electrical and Computer Engineering, University of Cyprus, Nicosia, Cyprus, in 2003 and 2009, respectively. Currently, he is a Assistant Professor with the Electrical and Computer Engineering Department, University of Nicosia, Cyprus. His research concentrates on the area of electronic design and testing. His research interests include design for testability, algorithms for high quality testing, high quality fault models and online testing.

    Maria K. Michael received the B.S. and M.S. degrees in Computer Science and the Ph.D. degree in Electrical and Computer Engineering from Southern Illinois University, Carbondale, in 1996, 1998, and 2002, respectively. She taught as a Lecturer with the Electrical and Computer Engineering Department, Southern Illinois University from 2001 to 2002, and as an Assistant Professor of computer science and engineering with the University of Notre Dame from 2002 to 2003. She is currently an Assistant Professor with the Electrical and Computer Engineering Department, University of Cyprus, Nicosia, Cyprus. Her research interests include test and fault diagnosis automation, semi-formal methods for logic and timing verification, symbolic techniques for test and verification (BDDs and SAT), design-for-testability, and fault tolerance and reliability of digital circuits.

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