Hardware resource utilization optimization in FPGA-based Heterogeneous MPSoC architectures

Abstract

Next generation FPGA circuits will allow the integration of dozens of hard and soft cores as well as dedicated accelerators in the same chip. These Heterogeneous Multiprocessor System-on-Chip (Ht-MPSoC) architectures will allow the design of very complex System-on-Chips (SoC) on a single FPGA chip and will fulfill modern application requirements, in terms of performance/energy consumption ratio. In this paper, we extend existing FPGA-based Ht-MPSoC architectures by considering sharing hardware accelerators among the cores. In these architectures, cores on the FPGA may have different resources that can be shared in different manners. To explore the large space of possible configurations of Ht-MPSoC on FPGA, designer needs a fast and accurate exploration tool. For this reason, a Mixed Integer Programming (MIP) model is also proposed to determine the Ht-MPSoC configuration that consumes the least HW resources while respecting the application execution time constraints. Using our MIP model, the design space of several hundreds of private and shared HW accelerators can be explored in a reasonable time with high accuracy.

Introduction

The increase in HW resources in the latest FPGA generation, makes it possible to implement extremely complex Heterogeneous Multi-Processor System-on-Chip (Ht-MPSoC) architectures. These architectures combine hardware and/or software cores, application-specific HW accelerators and communication units. The Xilinx Zynq 7000 Extensible Processing Platform (EPP) is an example of such architectures embedding a dual core ARM Cortex A9 processor and tens of thousands of programmable gate arrays [1]. Cyclone V from Altera [2] and SmartFusion2 from Micro-Semi [3] are other examples of Ht-MPSoC. These architectures include one or more hard-cores and up to 500 K of reconfigurable logic elements to build computational accelerators (Fig. 1).

Thanks to this reconfigurable area, it is possible to design either a Symmetric Ht-MPSoC (SHt-MPSoC), in which all the processors have the same number of private and shared HW accelerators, or an Asymmetric architectures (AHt-MPSoC) where HW accelerators attached to the different processors differ from one processor to the other. Fig. 2, Fig. 3, show two examples of Ht-MPSoC with 4 processors (P1 to P4). Fig. 2 highlights a 4-core SHt-MPSoC architecture, in which the processors have the same type and number of HW accelerators. In Fig. 2, each processor has one and the same HW accelerator (named Pr) and share m accelerators with the other processors. Fig. 3 gives an example of an AHt-MPSoC. In this architecture P1, P3 and P4 have each one a private accelerator (named Pr i). These private accelerators can be similar or different. P2 has no private accelerator. P1 and P2 share the same accelerator, named “Sh 1” in Fig. 3, whereas P2, P3 and P4 share another HW accelerator, named “Sh 2”. In an AHt-MPSoC, critical applications (or tasks for a multitasked system) are executed by cores with a large number of private accelerators. At the opposite, applications that are not critical are run by cores with small number (or not at all) private HW accelerators.

We think that AHt-MPSoC is a very promising class of architectures as it allows an efficient utilization of HW resources and provides high performances with less energy consumption [5]. However, their utilization increases even more the size of the design space of configurations to explore. Thus, it is necessary to provide to the designer a Design Space Exploration (DSE) tool to determine the best architectural configuration for a given set of concurrent applications. In addition, this tool plays an important role in the design flow of Ht-MPSoC architectures as it allows to determine the most efficient Ht-MPSoC configuration in a reduced time. This configuration is the one that requires the least FPGA resources and gives a reduced execution time and energy budget.

In the literature, very few works have been devoted to DSE tool for AHt-MPSoC. This is due to the fact that previous and current generation of FPGA circuits offer relatively few resources, in terms of logic elements, compared to ASICs. Thus, it was possible to explore the entire design space in relatively short time interval either by simulation or by simple analytical models. In other studies, the authors only consider SHt-MPSoC architectures in which all processors have the same number and type of accelerators. This approach limits the application of Ht-MPSoC and cannot effectively operate for high complex reconfigurable systems.

In the solution that we propose in this paper, we target next generation FPGA circuits with a high number of reconfigurable logic elements and their utilization in AHt-MPSoC architectures. In these architectures, the number of HW accelerators and their type may vary from one processor to another. Furthermore in our model, the applications executed by the processors may differ from one processor to another. Our solution is based on Mixed Integer Linear Programming (MIP) formulation to explore the very large space of possible configurations. Due to the complexity of finding an optimal enumerative solution, the proposed mathematical model allows the identification of a global minimum (i.e. area usage) in a reasonable time. This model was solved, after a process of constraints linearization, using CPLEX linear program solver.

The paper consists of 6 sections. In the next section, a survey on existing approaches in Ht-MPSoC is presented. In Section 3, we detail AHt-MPSoC architectures and discuss their benefits. In Section 4, we develop our MIP-based Design Space Exploration (DSE) for AHt-MPSoC. The next section presents the experimental results and the obtained performances of our AHt-MPSoC for real and synthetic benchmarks. Finally in Section 6, we give a conclusion and some possible extensions to make AHt-MPSoC more efficient.