Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes
Introduction
The variability and reliability of ICs are being endangered in the downscaled CMOS technology nodes. Time-zero variability effects such as Random Discrete Doping (RDD), Line Edge Roughness (LER), etc. result in a spatial spread on a device’s parameters [1]. On the other hand, time-dependent degradation, i.e. aging, gradually exacerbates/widens, and shifts the initial spread depending on the workload stress [2]. Most relevant, threshold voltage related failure mechanism is primarily associated to the Negative Bias Temperature Instability (NBTI) observed in p-channel transistors. The modeling of the NBTI degradation at process-, transistor-, and circuit-level is defined as one of the grand-challenges for the near-future, due to the downscaling transistor dimensions, higher electric field on the gate oxide, introduction of high-k metal gate, etc. [3]. NBTI can induce time-dependent variability, which adds on top of the initial time-zero variability [4]. Consequently, a device’s lifetime becomes widely distributed due to the NBTI-induced threshold voltage shift [5], e.g. 100 mV of , a channel current reduction of , and worsens with the downscaling nodes as the electrical fields increase [6].
Device times to failure become widely distributed due to the BTI-induced threshold voltage shift [5], [7]. Assuming a constant trap density in the oxide per unit area, gate area scaling reduces the number of traps per device, while it increases the average threshold voltage shift induced by each individual trap [8]. Deeply scaled planar FETs will contain only a few, randomly behaving defects, while the relative impact of a single defect may become substantial [9]. FinFET devices will have a larger area, hence more defects than a planar device of the same node, while BTI-induced variability is more dominant in FinFET devices [10]. Nonetheless, an individual charged defect can significantly shift the channel current of a nm-sized FET, causing threshold voltage () fluctuations in the form of RTN [11].
The stress-dependent nature of NBTI can cause a variation of regarding to the workload characteristic on a transistor’s gate [12]. However, the impact at the transistor-level propagates up to higher design levels via the gate delay (e.g. [13]), the critical path ( [14]), and the processor-level ( [15]). In addition, the replacement of the time-zero critical path by a non-critical path during a circuit’s lifetime occurs at substantial levels [14], [15]. Therefore, the modeling of workload-dependent NBTI aging for higher design levels is a crucial requirement.
The well-known transistor-level NBTI models are the statistical mechanics-based model [16], Reaction–Diffusion (R-D) model [17], [18], Trap-based model [5], and finally the Capture/Emission Time map-based model [19]. Simplified gate delay models [20], [21], [22], and the pre-characterization of gate delay look-up tables (LUTs) [18], [14], [23] have been proposed to propagate the impact to the netlist-level. However, these methods have suffered from loss of accuracy due to the first-order modeling of the gate delay degradation for only a few simple cell types, or the aging analysis considered only a limited set of standard cell library, and critical paths in a design. Reference [15] proposed a workload-dependent, instance-based, aging-aware library characterization as a scalable and accurate approach. However, the previous studies have been focusing on a single transistor, individual gates, SRAM cell and periphery, generic benchmark circuits or a general-purpose microprocessor.
In the first part of this work, we focus on a 32-bit adder block which is the main component of a representative processor datapath. For such an adder, we apply the main concept of workload-dependent, instance-based, aging-aware library characterization to obtain a comprehensive analysis of the NBTI aging at the block-level, presenting:
- 1.
Workload-dependent NBTI aging trends on 32-bit adder architectures (e.g. KoggeStone, LadnerFischer, etc.),
- 2.
Technology scaling of the NBTI aging in the commercial planar nm FET nodes based on the extracted CET map data based on the actual wafer measurements,
- 3.
Correlation of aging sensitivity to internal adder architecture topology parameters and representative workload variations.
4.Commercial-grade 28 nm planar and research-grade nm FinFET technology nodes,
5. Combinations of several FET channel materials (e.g. Si, SiGe, Ge, InGaAs)
The rest of the paper is organized as follows. Section 2 summarizes the related work. Section 3 explains the CET map-based NBTI model, and presents the workload-dependent, instance-based, NBTI aging-aware flow. Section 4 describes the experiments. Section 5 discusses aging trends from the points of architecture, technology scaling and workload.
Section snippets
Related work
This section explains the classification of the related work as shown in Fig. 1.
At the transistor level, there are major four models: statistical mechanics-based model [16], R-D model [17], [18], trap-based model [5], and Capture/Emission Time (CET) map-based model [19]. Statistical mechanics-based model [16] and R-D model [17], [18] assumed the NBTI recovery phase only due to H passivation, and had mismatches between the simulation and the experimental data (e.g. log(t)-like recovery). The
Workload-dependent, Capture/Emission Time (CET) map-based NBTI aging-aware flow
This study adapts the workload-dependent, instance-based, NBTI aging-aware library characterization approach [15] to analyze the NBTI aging on the block-level. Reliability of complex VSLI designs are required to be investigated under different task benchmarks. Transistor-level flows are not scalable from tens of devices to the systems consisting high number of gates, timing paths, complex signaling, multi-input gates, etc. [15]. Therefore, STA method is advantageous compared to the
Experimental setup
This study investigates the collective degradation behavior of individual devices in complex designs in the planar nm FET nodes with the state-of-the-art CET map-based model based on the extracted CET map data from actual measurements. Experiments target to study the impact of architectural topology, technology scaling and workload dependence. The setup environment is based on the workload-dependent, instance-based, NBTI aging-aware library characterization, which is integrated within
Results
This section presents the results of the NBTI aging simulations on adder architectures and ring oscillators in the downscaling technology nodes.
Conclusion
This study investigates the impact of the NBTI aging on 32-bit adders and ring oscillators in the downscaling technology nodes. First, the performance degradation of 32-bit adders is studied from the points of architecture topology, technology scaling, and workload dependence. Simulations are based on the extracted CET map data from the actual wafer measurements on the SiON nm and HKMG 28 nm planar FET nodes. State-of-the-art CET map-based NBTI model is integrated with the
Halil Kükner received his B.Sc. degree from Sabanci University, Istanbul, Turkey, in 2008; and his M.Sc. degree from Technische Universiteit Delft, Netherlands, in 2010; both in electrical engineering. He completed his Ph.D. study in the Circuits and Systems for ICT group at IMEC, Leuven, Belgium, in 2015, and also in the Department of Electrical Engineering of Katholieke Universiteit Leuven, Belgium. He is currently a Senior Design Engineer at the MKR-IC Mikroelektronik Ltd, Istanbul, Turkey.
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Halil Kükner received his B.Sc. degree from Sabanci University, Istanbul, Turkey, in 2008; and his M.Sc. degree from Technische Universiteit Delft, Netherlands, in 2010; both in electrical engineering. He completed his Ph.D. study in the Circuits and Systems for ICT group at IMEC, Leuven, Belgium, in 2015, and also in the Department of Electrical Engineering of Katholieke Universiteit Leuven, Belgium. He is currently a Senior Design Engineer at the MKR-IC Mikroelektronik Ltd, Istanbul, Turkey. He has the Best Paper Award at DTIS’11 conference. His research interests include the PDK development, IC design, BTI reliability of digital circuits, HW architecture, memory built-in self-testing, image/video processing, and motion estimation.
Pieter Weckx received his M.Sc. degree in nanoscience and nanotechnology from the Katholieke Universiteit Leuven, Belgium, in 2011. He is currently pursuing the Ph.D. degree with the Reliability Group of Interuniversity Microelectronics Center, Leuven, Belgium, and Katholieke Universiteit Leuven, Leuven, on the topic of modeling and simulation of time-dependent variability problems in nanoscaled electronic devices.
Sébastien Morrison received his B.Sc and M.Sc. degrees from the Université Libre de Bruxelles (ULB), Belgium, in 2011 and 2013 respectively. He has worked on reliability aspects of digital circuits at imec and is currently pursuing a Ph.D. at imec in collaboration with the Vrije Universiteit Brussel (VUB), Belgium. He is involved in the design of analog circuits to monitor noise sources such as thermal noise, flicker noise, RTN and BTI that affect devices in modern deeply downscaled technologies.
Jacopo Franco is a Senior Researcher at imec, Belgium. He received the B.Sc. and M.Sc. in Electronic Engineering from the University of Calabria, Italy, in 2005 and 2008 respectively, and the Ph.D. degree in Engineering from KU Leuven, Belgium, in Jan. 2013. His research focuses on the reliability of high-mobility Ge and IIIV channel transistors for future CMOS nodes, and on variability issues in nanoscale devices. He has (co-)authored 120+ papers and received the Best Student Paper Award at IEEE SISC (2009), and the EDS Ph.D. Student Fellowship (2012). He is also one of the recipients of the EDS Paul Rappaport Award (2011), and the Best (2012) and Outstanding (2014) Paper Awards at IRPS. He is serving as a committee member at IEEE IRPS and IIRW conferences.
Maria Toledano Luque has recently joined Samsung, South Korea, as a Senior Researcher. She is currently working on RMG for 7nm CMOS technology. She received the M.Sc. degree in Electrical Engineering in 2003, the M.Sc. degree in Physics in 2009, and the Ph.D. degree in 2008 from the Universidad Complutense de Madrid (UCM), Spain. After lecturing for 3 years at the UCM, she joined the Devices Reliability and Electrical Characterization Group of imec, Belgium, in 2011. Her activities included advanced electrical characterization of charge trap vertical flash memories, and FEOL reliability/variability research of future CMOS technologies. She has authored or co-authored more than 150 journal and conference papers, 3 book chapters and presented invited conference papers. She was serving as a committee member at the International Reliability Physics Symposium (IRPS) in 2013 and 2014.
Moon Ju Cho received the Ph.D. degree in materials science and engineering from Seoul National University, Korea, in 2007. She joined the reliability group of the Interuniversity Microelectronics Center (IMEC) in 2007. From 2007 till 2009, she performed a postdoctoral research at IMEC on theoretical modeling for oxide trap characterization. Since 2009, she has been working at the reliability group in IMEC as a researcher. Her current research is focused on the reliability of logic planar and multiple-gate MOSFETs, and tunnel-FETs.
Praveen Raghavan Dr. Praveen Raghavan obtained his Ph.D. from KU Leuven in 2009 and his Masters from Arizona State University, USA. He received his Bachelors Degree in Electrical Engineering from Regional Engineering College Trichy, India. In 2007, he was also a visiting researcher at Berkeley Wireless Research Center (BWRC), University of Berkeley, California. He is currently leads the group for design enabled technology exploration at IMEC. He is in charge of imec's research for evaluating the key power-performance-area (PPA) benefits of scaled CMOS technologies and beyond CMOS technologies.In his past he has been the lead architect of IMEC’s multi-gigabit software-defined radio baseband chip set. His research interests include DTCO, PPAC, Device modeling, design methodologies, reliability, variability and low power design. He has published over 150 conference and journal papers and holds more than 30 patents.
Ben Kaczer received the Ph.D. degree in physics from The Ohio State University, Columbus, OH, USA, in 1998. He joined the Reliability Group of Interuniversity Microelectronics Center, Leuven, Belgium, in 1998, where he is a Principal Scientist of advance electrical characterization and reliability. He has over 50 journal and conference papers. Dr. Kaczer received the OSU Presidential Fellowship and support from Texas Instruments, Inc. for his Ph.D. research. He was a recipient of three Best and one Outstanding Paper Awards at IRPS and the Best Paper Award at IPFA. He is currently serving on the IEEE T. Electron Dev. Editorial Board.
Doyoung Jang received the Ph.D. degree in Nanoscience & Nanotechnology from INP Grenoble, Grenoble, France and Korea University, Seoul, Korea in 2012. He is currently a Researcher at imec, Leuven, Belgium, involved in the device modeling and characterization for Design-Technology co-optimization in advanced CMOS technology.
Kenichi Miyaguchi received B.E. and M.E. degrees in electrical and electronic engineering from Kyoto University, Japan, in 1997 and 1999, respectively. In 1999, he joined Mitsubishi Electric Corporation, Kamakura, Japan, where he was engaged in research and development of microwave and millimeter-wave ICs for radar and satellite communication. In 2007–2012, he worked at Texas Instruments Japan to design analog/mixed-signal ICs for power management. Since 2012, he has been involved in research in advanced CMOS technology in IMEC, Belgium. Mr. Miyaguchi is a member of the IEEE.
Marie Garcia Bardon received her M.Sc. degree in electromechanical engineering from Université Catholique de Louvain, Louvain-la-Neuve, Belgium, in 2004, and her Ph.D. degree from Katholieke Universiteit Leuven, Belgium, in collaboration with Interuniversity Micro-Electronics Centre (IMEC), Leuven. She is currently a Research Scientist in the Technology Aware Design Group at IMEC, where her work involves the simulation and compact modeling of advanced devices for digital circuit applications.
Francky Catthoor received the Engineering and Ph.D. degrees in electrical engineering from Katholieke Universiteit Leuven, Belgium, in 1982 and 1987, respectively. He has been the head of several research domains in the area of high-level and system synthesis techniques and architectural methodologies with the Interuniversity Microelectronics Center, Leuven, since 1987. He is a part-time Full Professor with the Department of Electronic Engineering, K.U. Leuven.
Liesbet Van der Perre received the M.Sc. degree in electrical engineering from the K.U. Leuven, Belgium, in 1992. The research for her thesis was completed at the Ecole Nationale Superieure de Telecommunications in Paris. She graduated summa cum laude with a Ph.D. degree in electrical engineering from the same university in 1997. Currently, she is program director for IMEC’s green radio program, comprising cognitive reconfigurable radios and mm-wave communications. Liesbet is a professor at the K.U. Leuven. She has over 250 scientific publications published in conference proceedings, journals, and books.
Rudy Lauwereins is vice president of IMEC, Smart Systems Technology Office, guiding the strategic research decisions in vision and telecommunication systems, and in (bio) medical and lifestyle electronics. He is a part-time Full Professor at the Katholieke Universiteit Leuven, Belgium. He had obtained a Ph.D. degree in electrical engineering in 1989. Professor Lauwereins has more than 380 publications in international journals, books and conference proceedings.
Guido Groeseneken received the Ph.D. degree in applied sciences from Katholieke Universiteit Leuven, Belgium, in 1986. He joined the Interuniversity Microelectronics Center, Leuven, in 1987. He is responsible for research in reliability physics for deep-submicron CMOS technologies and in nanotechnology for post-CMOS applications. He is a part-time Full Professor with the Department of Electronic Engineering, K.U. Leuven.