Novel low power reversible binary incrementer design using quantum-dot cellular automata
Introduction
In digital world, at hardware level, the most computational hurdle is the energy dissipation. Landauer [1] has proved that irreversible computation will have kBTln 2 joules of dissipated energy due to loss of single bit information. This dissipated energy is considered as the lower bound to computation. Here, kB and T holds for Boltzmann's constant and the computing temperature [2], [3]. By resisting the loss of information bits, energy dissipation can be preserved. The most promising way out is reversible computation [3], [4]. The computation in reversible circuit is carried out at logic level using bijective mapping, i.e., one-to-one mapping between input to output. Reversible circuits have no loss of information. The bijective mapping improves the observability and the controllability of the circuit [3], [4]. It is expected that complementary metal-oxide-semiconductor (CMOS) technology will reach to its scaling limitation in next decade. Thus new nanotechnologies are being explored that has reduced dimensions and novel properties. As an alternative, quantum-dot cellular automata (QCA) technology has been proposed for CMOS technology. QCA is transistor-less technology, which combines the advantages of quantum dot and cellular automata logic together. QCA have several potential advantages like high density, fast operating speed, and very low power consumption [5], [6], [7], [8]. In QCA, each bit of information is accumulated by using charge on electrons, present within QCA cell. Electrostatic interaction between QCA cells in a QCA circuit, caused transmission of bits through the circuit. Information processing technique used in QCA creates different and advance way to design logic circuit than that of CMOS circuit [9], [10], [11], [12]. This paper deals with the reversible logic based design methodology of binary incrementer circuit and its implementation through QCA technology for the first time. The designs are achieved by employing Peres gate. The proposed QCA layouts and their simulation are executed through QCA Designer tool [13], which is a Bi-stable simulator engine.
Binary incrementer is essential to perform the increment operation on binary numbers in arithmetic logic unit. The irreversible nano-scale device originates high power dissipation. The solution is to employ reversible logic circuit, which has low power dissipation, i.e., ideally zero. Ultra low power dissipation of QCA device pledges the dominating implementation of reversible circuit at nano-scale than that of CMOS based design [2].
The contributions of this paper are as follows:
- (1)
QCA based design and implementation of Peres gate and reversible half-adder circuit.
- (2)
Design of n-bit reversible binary incrementer circuit using Peres gate.
- (3)
QCA implementation of proposed reversible incrementer circuit. The implementation is achieved for the first time.
- (4)
To achieve the QCA layout of half-adder and incrementer circuit, the same QCA circuit of Peres gate is employed.
- (5)
The estimation of quantum cost for both in quantum gate based technology as well as in QCA based technology is performed and also compared. The comparison shows the dominating design in QCA.
- (6)
Stuck-at-fault analysis for Peres gate is explored.
- (7)
Single missing/additional cell based defect analysis for the QCA circuits are performed.
- (8)
The power dissipated by the proposed QCA layouts is estimated.
- (9)
The accuracy of all the circuits under thermal randomness is tested and excelled.
- (10)
The circuits are evaluated based on parameters like logic gate, circuit density and operating speed. The simulation outputs are verified by the truth table.
The paper is structured as follows. Section 2 describes the different devices of QCA. In Section 3, the design and implementation methodology of proposed binary incrementer circuit in QCA platform are demonstrated. In Section 4, the simulation results are verified through truth table. Section 4 also deals with the estimation of dissipated power, defect analysis, quantum cost estimation and design accuracy under thermal randomness. The conclusion is finally summarized in Section 5.
Section snippets
QCA devices
In QCA, each QCA cell is represented by using a square structure as shown in Fig. 1a. Each square is prepared with four quantum dots [10]. Every dot can holds only single electron. First two free electrons are pushed into the QCA cell, which are then moved to the diagonal position due to their repulsion within the cell. The arrangement of electrons are used to represent the logic value “0” and logic value “1” as shown in Fig. 1a. The basic device of QCA circuit is majority voter (MV). It
Reversible binary incrementer using QCA
Reversible binary incrementer design using QCA is explored in this section. This section is organized as follows. The overview of reversible circuit and binary incrementer circuit are illustrated in Section 3.1. In Section 3.2, QCA based design of Peres gate is demonstrated. Section 3.3 deals with the design of reversible half-adder based on Peres gate and it's realization through QCA. Related works are explored in Section 3.4. Finally, novel n-bit reversible binary incrementer is achieved in
Result and discussions
All the design of proposed binary incrementer and their implementation are carried out in QCA Designer-2.0.3 tool [13]. The parameters which are used in simulation of proposed QCA circuit, is shown in Fig. 13. The size of each QCA cell is 18 nm × 18 nm. The circuit complexity of proposed QCA layout is shown in Table 7.
From Table 7, it can be observed that the area usage percentage is decreasing by raising the area of the designs. As because, the area usage percentage is estimated by multiplying
Conclusion
This paper presents the QCA based realization of n-bit binary incrementer, like 1-bit binary incrementer, 2-bit binary incrementer, etc. using reversible logic for the first time. This paper also outlines the design and implementation of reversible half-adder in QCA. To design the incrementer circuits, identical QCA layout of Peres gate is utilized. All the designs are evaluated in terms of logic gates, circuit density and latency, which confirms the higher device density and low delay. The
Acknowledgments
The authors are grateful to the University Grants Commission, India, for providing with the grant for accomplishment of the project under the UGC Major Project File no. 41-631/2012(SR).
Jadav Chandra Das received M.Tech degree in Multimedia and Software Systems from West Bengal University of Technology, West Bengal, India, in 2011. Presently he is an assistant professor in the Department of Computer Science and Engineering, Swami Vivekananda Institute of Science and Technology under West Bengal University of Technology, Kolkata, India. His research interest includes image processing, cryptography and QCA based image processing.
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Jadav Chandra Das received M.Tech degree in Multimedia and Software Systems from West Bengal University of Technology, West Bengal, India, in 2011. Presently he is an assistant professor in the Department of Computer Science and Engineering, Swami Vivekananda Institute of Science and Technology under West Bengal University of Technology, Kolkata, India. His research interest includes image processing, cryptography and QCA based image processing.
Debashis De received M.Tech degree in Radio Physics & Electronics in 2002. He obtained his Ph.D. (Engineering) from Jadavpur University in 2005. He worked as R&D Engineer of Telektronics. Presently he is an associate professor in the Department of Computer Science and Engineering of West Bengal University of Technology, India and Adjunct Research Fellow of University of Western Australia, Australia. He was awarded the prestigious Boyscast Fellowship by Department of Science and Technology, Govt. of India to work at Herriot-Watt University, Scotland, UK. He is also awarded Endeavour Fellowship Award during 2008–2009 by DEST Australia to work in the University of Western Australia. He received Young Scientist award both in 2005 at New Delhi and in 2011 at Istanbul by International Union of Radio Science, H.Q., Belgium. His research interest includes location management and power consumption control in mobile network and low power nano device design for mobile application and disaster management.