Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor

Abstract

Scaling new-silicons to nano-scale era has brought more integration, high performance and low power consumption while the reliability becomes a serious challenge for integrated circuits technology. Therefore, reliability awareness has become essential in early stages of integrated circuit design. Since many of modern chips scrimmage with the limited power budget and traditional techniques such as N-Modular Redundancy (NMR) is not efficient for non-uniform fault tolerance, accurate analyzing of the reliability of different hardware components or application parts is necessary. Transient and soft errors which are resulted from cosmic rays strike and Process Voltage and Temperature (PVT) variation are known as main sources of unreliability. Recently, Architectural Vulnerability Factor (AVF) is widely used for analyzing the reliability of a processors. In this paper, we have introduced a new metric named as Instruction Vulnerability Factor (IVF) which is used for fast, accurate, and recurring AVF estimation. Special scenarios have been developed which enable us to utilize exhaustive fault injection for precise IVF calculation for a given processor instruction set. IVFs of a special instruction considers the vulnerability of pipeline stages while executing the instruction. Finally, a simple equation has been derived for AVF estimation based on running instructions. Our experimental results which are extracted by our Configurable Reliability Analysis Framework (CRAF) confirm the accuracy of presented AVF estimation method. Moreover, IVF can be employed by reliability aware compilation or online AVF estimation techniques.

Introduction

Although shrinking the technology feature size to nano-scale leads to lower power consumption, higher performance, and more integrity, the reliability of new silicons is a new important challenge. Nowadays, soft errors are an important concern in designing reliable nano-scale integrated circuits and have emerged as a key challenge to microprocessor design. With dimensions of the circuit elements getting closer to countable atom diameters, circuits become more vulnerable to electronic noises which are generally resulted from high-current power supplies, internal radiations from decomposition of heavy metal mixed with utilized metallization, or a hit by external high-energy particle [1]. These random effects can cause a current pulse at an internal node of the circuit and flip the state of the logic when the induced charge is accumulated to a sufficient amount. Such a pulse can lead to a temporary change in the logic level of the struck node and cause a Single Event Transient (SET), or the particle may hit a storage element and change the stored value and cause a Single Event Upset (SEU).

Although Mean-Time-To-Failure (MTTF) is a well-known measure for reliability analysis and covers all failure mechanisms including diffusion, aging, and packaging defects, Failure In Time (FIT) is a more specific measure for soft errors. FIT which indicates how many errors in one billion operating device hours are expected, not only depends on the device itself, but also on the operating conditions (supply voltage, temperature) and the device’s location (position on earth surface, altitude, or maybe in space). FIT is separated into two factors [2]: Raw Error Rate which depends on the environmental conditions and Architectural Vulnerability Factor (AVF) that reflects the susceptibility of design to soft errors. AVF is defined as the possibility that a soft error (transient error) eventually leads to a visible error at program output. This metric can be computed as a portion of the important bits in the structure that are required for Architecturally Correct Execution (ACE) to the total number of bits of the structure. Since AVF is independent of environmental conditions, it is suitable for comparison between reliability of different architectures and AVF awareness at early design stage is greatly helpful to achieve a trade-off between system performance and reliability.

Three well known methods for AVF computation are reported [3]: analytical models, performance models (simulators), and statistical fault injection (SFI) models. In AVF estimation by analytical models, Little’s Law is applied to ACE bits and the average number of ACE bits in the structure is calculated. In the early stages of design which neither a performance model nor a detailed RTL model is available, this technique can be useful. Performance model identifies ACE and un-ACE bits of the objects flowing through the structure and gets the fraction of time in which a bit contains ACE state as the AVF of the bit. This analysis requires an in-depth understanding of the micro-architectural states of the processors. The last AVF computation method, SFI, performs bit flips into RTL model of the processor and the AVF of the structure is then estimated as the fraction of mismatches divided by the total number of bit flips [4], [5]. Although SFI is a very powerful technique and can compute AVF without understanding the processor architecture, unfortunately it can be used only in detailed models, such as RTL, and is usually much slower than performance models. Indeed, exploiting this method for AVF computation requires a large amount of simulation time to cover efficient number of injected errors.

There are many researches about efficient AVF estimation [2], [6], [7], [8], [9], [10], [11], [12] and mostly the AVFs of small structures such as Instruction Queue (IQ), Reorder Buffer (ROB), Load/Store Queue (LSQ), and eventually Register File (RF) have been estimated. In fact, performance models for AVF estimation are time consuming methods and are not appropriate for large structures such as a whole processor. From another point of view, all of these hardware structures are sequential parts and their states have been traced for ACE analysis. With bit flips which are introduced only into sequential parts, soft errors in combinational parts and their properties in fault masking have been neglected. While for moderate nano-scale silicons, transient errors at combinational nodes must be taken into account [13].

This paper introduces a new reliability metric named as Instruction Vulnerability Factor (IVF) which is utilized for fast and accurate AVF estimation. We have proposed novel scenarios for IVF extraction which enables us to exploit exhaustive fault injection in a reasonable simulation time to capture more accurate IVFs. Our extensive simulations and verifications prove that IVF values which are calculated once for a given processor’s Instruction Set Architecture (ISA) carry the accuracy of fault injection. Then, we have derived a simple analytical equation for AVF estimation based on the IVFs of running instructions. Our AVF estimation method is very fast and our experimental results confirm that its accuracy is comparable to AVF estimation by fault injection.