CNFET-based approximate ternary adders for energy-efficient image processing applications

Abstract

Nowadays, low power design has attracted more attentions. This purpose is achieved through some techniques such as low-power design methods, multiple valued logic and more recently by approximate computing. Carbon nanotube field-effect transistor (CNFET) is an appropriate candidate device for low-power multiple valued logic applications. In approximate computing, reducing the precision of arithmetic blocks leads to reduction in power consumption. In this paper, two approximate CNFET-based ternary full adder cells are proposed. The proposed designs considerably reduce the design complexity and the number of transistors by utilizing the unique properties of CNFETs as well as the switching logic style. The simulation results demonstrate that the proposed approximate designs improve the delay, power and energy dissipation by about 90% as compared to their exact counterparts. Also, as the adder cells are commonly used in the reduction step of multiplier circuits, the efficiency of the proposed cells is investigated in the structure of ternary multipliers through the normalized error distance and power-error tradeoff metrics. Moreover, as the approximate circuits are used in image processing applications, an inexact ternary multiplier is utilized for pixel by pixel image multiplying and the results are compared with the exact ones. According to the simulation results, the proposed inexact methods enhance the performance of arithmetic circuits while maintaining the required accuracy for such applications.

Introduction

Nowadays power efficiency is an important factor for designing computational circuits. This is especially more of an interest for embedded and mobile applications to save energy. Energy consumption is also very important in media processors such as image and audio processors. In addition, as the transistor dimensions scale, the power density may not decrease and chips become hotter when using traditional solutions. Excessive power densities on chips lead to performance degradation and failure and extremely costly packaging methods are required. Therefore new design strategies and computational methods are needed.

One of the most interesting solutions for reducing the static power of computational circuits is to use approximate computing. Approximate or inexact computing is a class of techniques which relaxes the precision of a circuit with the aim of reducing the power consumption and enhancing the performance [1], [2].

Inexact computing can be applied for implementing bio-inspired systems or any system which involves human-like information processing such as control, diagnosis, pattern recognition, signal processing, etc. Fuzzy, neuro, and evolutional computing are some sub-categories of the inexact computing. The core of commonly used multimedia applications consists of digital signal processing (DSP) blocks. Many of these DSP blocks implement algorithms and procedures, in which the final output is either a video or an image for human representation and analysis. Various applications such as image processing and multimedia can endure inaccuracy and errors in computation and generate effective and utilizable results. Accurate procedures and methods are neither always advantageous nor effective in such applications. Approximate computing can be efficiently utilized in such applications as the limitations of human vision allow us to have an inexact circuit for such applications [3].

On the other hand, the consequent challenges of scaling the feature size of MOS transistors such as short channel effect, high leakage power, degraded gate control and parametric variations forces us to replace MOSFET with the alternative emerging technologies [4]. Quantum-dot cellular automata (QCA), single electron transistor (SET) and carbon nanotube field effect transistors (CNFET) are some of these emerging nanotechnologies [5], [6], [7]. However, CNFET seems to be the most feasible candidate due to its unique features and its inherent similarities with MOS transistors. In addition, one dimensional band structure and near ballistic operation of CNFET enhances the performance and energy efficiency of the CNFET-based circuits as compared to the MOSFET-based designs [7]. Accordingly, CNFET can be effectively used for designing energy-efficient integrated circuits.

In addition to approximate computation and using emerging low-power devices such as CNFET, another way for reducing the energy dissipation is to utilize multiple valued logic (MVL) i.e. deployment of more than two logic levels for computation. Using MVL design leads to reduction in area, pin count and the number of interconnects because of carrying more information in MVL logic as compared to binary logic [8], [9]. Studies have shown that using radix e (≈2.718) for computation leads to the most system-level efficiency [10]. However, due to the physical hardware restrictions, the radix of arithmetic operations should be an integer value and we could use the nearest of them to the optimum radix. Therefore, ternary (radix 3) operations could be more of an interest to reach less complexity [11].

Full adder cell is one of the basic blocks of arithmetic circuits and improving its performance considerably enhances the performance of other larger blocks such as multipliers. To reach energy efficiency in the proposed full adders, the aforementioned solutions including approximate computing, the unique features of the CNFET nanodevice and ternary logic design are employed. Accordingly, in this paper two low-power CNFET-based approximate full adders for ternary logic are proposed.

The rest of this paper is organized as follows: Section 2 includes the review of approximate computing, its definition and basic concepts as well as a brief overview of the CNFET device. Section 3 represents the proposed designs in detail and the comprehensive simulation results and comparisons are given in Section 4. Some important applications of these designs in image processing are given in Section 5 and the finally Section 6 concludes the paper.