Problems and challenges of emerging technology networks−on−chip: A review
Introduction
Technology advances have enabled the stack of many different cores in a multi−layered single chip with homogenous or heterogeneous processing elements [1], memories [2], Intellectual Properties (IPs), etc. For such chips, intra−communication was a bottleneck. In fact, conventional buses were not able to keep up with the bandwidth and the complexity of recent multi− or many− processors chips. Due to the heterogeneity of recent chips and the large number of internal cores such as contemporary systems−on−chip (SoC), system designers have to deal with multi−clock and multi−power domains, long wires and many other problems that came to surface at earlier design stages.
Another bottleneck pointed by the industry is the mismatch abstraction between cores and buses. When higher abstraction levels were meant to minimize the details to handle by system designers, interconnect logic forced them to design functional cores or IPs with interconnect constraints in mind. System designers were forced to work at lower levels of abstraction and thus, raised a question if it was trustworthy to rely on high integration technology benefits. Many industry actors, e.g. ARM with its AMBA protocol or the VSI Alliance effort, have focused at that time, on matching cores to buses [3].
The essence of networks−on−chip (NoC) paradigm, promoted 14 years ago [4], is when scaling to such heterogeneity and/or cores’ dimension number, intra−chip interconnection concept shifts from conventional buses to sophisticated networks. The potential of the NoC concept resides in part in the total separation of computation from data transportation. This will allow a decoupled design approach even at earlier design stages. By consequence, systems’ designers, working at the top−level of the project, can progress in the design processes of the desired SoC without concerns about protocol and width conversions, also about multi−clock and multi−power domains. Heterogeneity and conversion problems are simply handled by the NoC layer. Key contributions to a basic, bus−based, chip design flow, are in performance, power consumption, die size and project design time. The last two contributions are key factors that allow NoC concept to persevere and to be adopted in industry [5].
A necessary practice in SoC design is to reuse legacy IPs whether they are locally developed or externally licensed but when they are put together in the same design the reuse potential is not guaranteed. The reason is that they can be clocked at different frequencies or communicate with different protocols. In this case, they need to be re−edited and modified before they are used within the design. However, this task is time consuming, difficult to realize and in some cases infeasible. In addition, if the number of these IPs increases, the reuse potential is further diminished. NoC tools played a significant role to overcome these issues. In fact, they can offer a very flexible and automated design environment to link this variety of IPs without editing them [6], [7], [8].
An investigation conducted by third party economic experts has shown realistic revenue benefits obtained from NoC based system−on−chip (SoC) in the industry. The study provided precise advantages observed in industry among them the reduction of the wiring area, the logic gates number and the project design time. This also explains the obtained profit margin [9]. There are several commercial examples of NoC solutions such as FlexNoC Physical [6], [7] and SonicsGN [10]. Some of the other demonstrative examples are the actual commercialized general−purpose high performance processors. In fact, many of them represent the spirit of such adoption like the IBM Power8 processor [11] or the Tilera TILE64 [12].
Table 1 (column 1 and 2) shows a résumé of realistic problems faced by industry with bus− or crossbar− based large designs while the third column presents principal enhancements brought by the NoC paradigm to this type of designs [13]. Note that the objective behind Table 1 is to present NoC as an alternative to buses and crossbars not as a systematic replacement. Buses and crossbars have their intrinsic advantages compared to NoC and still are suited for a multitude of applications. Readers can find other interesting comparison tables between buses/crossbars and NoC for different design styles and with a variety of metrics in the works of Bjerregaard and Mahadevan [14] and Yoo et al. [15] (Refer to the fifth chapter).
To the best of our knowledge, the available NoC surveys and reviews, despite of their high quality, are outdated [16], [17] or do not provide an extensive classification of emerging technology NoC challenges [18], [19], [20]. However, we stress at the fact that such surveys and research papers remain our principal source of, whether inspiration or information to develop this survey.
There is also an underestimated challenge for both conventional and emerging technology NoC that is security. Only few works have discussed security concerns related to NoC. Moreover, fewer works tried to survey them. As NoC are the shared medium to circulate data among the system's IPs, they can play a significant role on the protection of their own systems. For example, installing protection mechanisms at the NoC level will allow the exemption of other important resources such as the systems’ CPUs from doing this task. On the contrary, there is also another interesting hypothesis assuming that NoC can be a threat for their own systems. In this particular case, new protection methods have to be developed.
Additionally, it is very common that previous surveys omitted the industry role in the evolution process of a new paradigm such as the NoC one. This is a misplaced assumption as the industry played a significant role on the evolution of the NoC paradigm especially in the case of CAD tools. In the future, this role will be of an important interest especially in the particular case of emerging technology NoC.
Overall, the main goals of this survey are to:
- i)
Analyze the importance of the NoC concept and adoption from an economical and industrial perspective.
- ii)
Review and discuss the research challenges as regard classical and emerging technology NoC.
- iii)
Highlight the potential research directions in the field with emphasis to the security challenge.
The remaining of the survey is structured as it follows: we first discuss the evolution of the NoC concept from an industrial perspective in Section 2. We classify the related surveys and review the basics of emerging technology NoC in Section 3. Section 4 initiates a discussion about the NoC current and future challenges. The industrial perspective is also considered. Finally, Section 5 concludes the paper.
Section snippets
The landscape of the NoC concept in industry
In this section, we examine the evolution of the NoC technology from an industrial perspective. We first present the major difficulties that faced the NoC industry to enter into the SoC marketplace. Second, we will discuss the particular case of a NoC solution provider, Arteris.
Several factors have limited the penetration of commercial NoC into commercialized SoC. Here is a distillation of the major ones:
- i)
The SoC industry was focused on usual and well known key factors such as reaching the
Related surveys
As one of the main objectives behind this effort is to provide an overview of recent NoC proposals from both industry and research with emphasis to emerging technology NoC, we only give the architectural principals of emerging technology NoC. The purpose is to highlight the differences between emerging technology NoC and the conventional ones and later to point out challenges that may rise from them. We study in the next paragraph the available surveys and textbooks in the NoC domain. The
Conclusion
Emerging technology NoC are very promising in terms of data throughput, latency and power consumption but there are still open issues and challenges to overcome. Through this effort, we studied common challenges of conventional and emerging technology NoC with a particular focus on the security one. Furthermore, we investigated the specific challenges for 3D NoC, Optical/Photonic NoC, Wireless NoC and RF−Interconnect.
For 3D NoC, the study of the relation between TSVs failure and 3D NoC's
Acknowledgements
The authors would like to thank Jim Handy from Objective Analysis and Kurt Shuler from Arteris for the NoC industry insights.
Ahmed Ben Achballah (1984) received the B.Sc. in electronics from the Faculty of Science of Bizerte in 2007, M.Sc. and Ph.D. in electronics from the National Institute of Applied Sciences and Technology of Tunis (INSAT) in 2009 and 2016, respectively. Currently, he is a full time educator with the Higher Institute of Information Technologies and Communication (ISTIC Borj Cedria, Tunisia) and researcher at the Advanced Systems Lab (LSA, Tunisia Polytechnic School). His research interests include
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Ahmed Ben Achballah (1984) received the B.Sc. in electronics from the Faculty of Science of Bizerte in 2007, M.Sc. and Ph.D. in electronics from the National Institute of Applied Sciences and Technology of Tunis (INSAT) in 2009 and 2016, respectively. Currently, he is a full time educator with the Higher Institute of Information Technologies and Communication (ISTIC Borj Cedria, Tunisia) and researcher at the Advanced Systems Lab (LSA, Tunisia Polytechnic School). His research interests include networks−on−chip design methods as well as high level synthesis.
Slim Ben Othman (1980) received the Dipl.-Ing and M.S. degree in electrical engineering (industrial data processing and automatic control specialty) from the National Institute of Applied Science and Technology (INSAT), Tunisia, in 2004. In 2011, he obtained his Ph.D. in industrial data processing from INSAT. Currently, he is a research member at Laboratory of Advanced Systems in the Polytechnic School of Tunisia. Since 2006, he has been a professor assistant in the department of electrical engineering, Higher Institute of Medical Technologies (ISTMT), Tunisia. His main research interests include methodologies and architectures of FPGA-based embedded systems design controllers.
Slim BEN SAOUD (1969) received the electrical engineer degree from the High National School of Electrical Engineering of Toulouse/France (ENSEEIHT) in 1993 and the Ph.D. degree from the National Polytechnic Institute of Toulouse (INPT) in 1996. He joined the department of Electrical Engineering at the National Institute of Applied Sciences and Technology of Tunis (INSAT) in 1997 as an assistant professor. He is now Professor and the Leader of the “Embedded Systems Design Group” at INSAT. His research interests include Embedded Systems Architectures, real-time solutions and applications to the Co-Design of digital control systems and SpaceWire modules.