Lightweight chaotic image encryption algorithm for real-time embedded system: Implementation and analysis on 32-bit microcontroller
Introduction
Communicating digitised form of visual information among transmission network has happened to be an essential need of the present world [1]. The presence of intruders in the communication medium necessitates the security solutions to protect the information from unauthorised access. Medical images like X-rays are the grayscale images that demand high security. One solution called cryptography [2] keeps the image visible after hiding its readability feature through a process known as encryption. The other solution called steganography [3], hides the image behind a cover by the process of embedding and leaves the image visible to all in the form of stego cover. The cover used is an image; it has been referred as image steganography. Both techniques are equally useful regarding securing the information being communicated from the perception of unauthorised persons. Many techniques have been found in the literature for encryption [2] as well for embedding [4].
The encryption techniques that are exclusively designed for extremely resource-constrained embedded devices like microcontrollers are classified as LightWeight Cryptography (LWC) [5]. The typical lightweight property of these algorithms has been warranted by its less complex operations [6], which in line fallout in low demand on memory and execution time in an attempt to meet the requirements of real-time applications. At the same time, the lightweight algorithms must also meet out the security level obligated by the application. Many lightweight schemes are found in the literature for encrypting text [7] and multimedia information [8] like images [9]. Text-based implementations have been carried out on a wide variety of embedded devices ranging from 8-bit to 32-bit microcontrollers [7].
Reconfigurable devices like Field Programmable Gate Array (FPGAs) [10] have been the choice for many imaging applications on the embedded platform. Compared to microcontrollers, FPGAs provides more storage space for applications and data with high performance. Regarding tradeoff among cost and performance, microcontrollers are found in all real-time applications providing low cost and low power solutions [11]. ARM-based microcontrollers are widely used in many security applications especially in the field of cryptography. Although microcontrollers are competent in handling variety of cryptographic algorithms, literaturehas accounted memory as a major bottleneck for the use of microcontrollers in image-based security applications. Grayscale images represented in digital form may contain two-dimensional arrays with a value of each array element (grayscale intensity value of the pixel) ranging between eight zeros and eight ones (00 to FF). This ensures the likelihood of using Images with grey scale resolution as the optimal choice for imaging applications with microcontrollers.
Chaos-based systems are highly appreciated for the design of cryptosystems owing to the true level of randomness they provide [12], [13]. The simplest form of a chaotic system can be obtained by one-dimensional (1D) discrete logistic map [14] as given in Eq. (1).
The above Eq. (1) uses the initial condition, . The chaotic range of 1D logistic map is decided by the control parameter, [15]. Based on the nature of 1D logistic equation, the output reaches a full saturated value when ′r′ is closer to 0. As per literature [14], better randomness in its output can be achieved while keeping the initial value X0 close to 0 and r value close to 4.
These systems operate on fractional inputs (floating point values) and produce the results again in fractional form. Floating point arithmetic is supported by modern microcontrollers via IEEE 754 representation format [16] as shown in Table 1. This is made feasible either by software through floating point library or by additional Vector Floating Point (VFP) hardware coprocessor unit.
Feasibility of implementing logistic map on 8-bit AVR microcontroller using Arduino board was discussed in work done by Serna [17]. Chaotic logistic map based secure data communication was made feasible using Arduino board by Zapateiro et al. [18]. However, no analyses on code size and execution parameters were carried out in the reported works [17], [19]. Murillo-Escobar et al. [20] realised a chaotic text encryption system and analysed its performance using a 32-bit microcontroller. Despite its resource constraints, researchers have already proven the ability of ARM-based microcontrollers in managing image-based security algorithms on steganography [11]. Notwithstanding the fact that image steganography is successful for implementation on portable embedded devices such as mobile phones [21], image encryption on ARM architectures are hard to be found in the literature.
The major contribution of this paper relies on the development of a new lossless image encryption algorithm using reversible lightweight operations. Further, generation of chaotic keys that fulfils the required security level using a microcontroller with single precision floating point support is also achieved. A detailed evaluation of the performance and security aspects of the proposed lightweight chaotic image encryption algorithm was also carried out on a 32-bit microcontroller to ensure its suitability for real-time embedded applications.
Murillo-Escobar et al. [20] showcased the appositeness of the 32-bit microcontroller in handling the chaotic discrete logistic map to generate keys to be used for the encryption process. They presented a good set of performance analysis of their chaotic encryption scheme on an embedded platform using a 32-bit microcontroller. Their encryption scheme was customized to handle only text information. Hence, developing a lightweight chaotic scheme exclusively tailored to encrypt images using an embedded device like microcontroller is desirable.
A chaos-based scheme to encrypt grayscale images was presented by Fu et al. [22]. This image encryption scheme utilized the initial conditions and control parameters of the Chebyshev and Arnold Cat map as its secret keys. The subkeys for the permutation stages 1 and 2 were generated by iterating the discretized Chebyshev and Arnold Cat map respectively. The implementation platform was said as a computer having Intel Core2 Duo processor running at 2.4 GHz with 2 GB memory. Although a wide range of security analysis was done on the proposed algorithm, their claim on the suitability of the work for real-time applications was only based on the speed performance of a general purpose computer system. Instead, performance evaluation when carried out on a resource-constrained embedded hardware device such as microcontroller would be more appropriate to find the aptness of the algorithm for real-time applications.
The algorithm proposed by Bahrami and Naderi [23] encrypts grayscale images through lightweight operations. This was implemented using the Matlab software on a desktop system with good security analysis. Knowing the fact that lightweight algorithms are the one targeted towards the implementation on a resource-constrained embedded platform, this work fails to analyse its lightweight performance on embedded hardware.
To overcome these shortcomings, this paper enlightens an attempt that combines the development of a lightweight grayscale image encryption algorithm using chaotic keys and its realization on a 32-bit microcontroller platform. Further, a wide analysis on security aspects and hardware performance validate the proposed algorithm for real-time embedded applications.
Section snippets
Proposed algorithm
The proposed image encryption algorithm is a lightweight scheme which utilises the 1D chaotic map along with lightweight operations. The major blocks involved in producing encrypted and decrypted images as per this chaotic lightweight image encryption algorithm are displayed in Fig. 1. The plain arrows represent the path for encryption while the shaded arrows direct the decryption process. The block with dotted lines symbolises the intermediate result whereas; the blocks with names in bold
Experimental result analysis
This section presents the results of various analyses concerned with the security level of the proposed algorithm and its performance under the 32-bit microcontroller platform. Initially, the randomness of the generated chaotic keys was tested using the NIST test suite. In addition, the security level of the proposed algorithm was tested through a set of analyses such as visual quality, key sensitivity, encryption quality, randomness, statistical and differential parameters in addition to
Conclusion
A chaotic lightweight algorithm to encrypt grayscale images and its implementation on 32-bit microcontroller was presented in this paper. The security level of the proposed algorithm was substantiated through a set of statistical and attack analysis. The ability of 32-bit microcontroller in handling image data and discrete chaotic function was proved by comparing the performance metrics regarding execution time and throughput with the results available in the literature. The smaller footprint
Siva Janakiraman received his B.E. Degree from Bharathidasan University, Tiruchirapalli, India in 2003. He received M.Tech. Degree in Embedded Systems and Ph.D. Degree from SASTRA University, Thanjavur, India in 2007 and 2017 respectively. He is currently working as an Assistant Professor in the School of EEE, SASTRA University. His research interests include embedded system and information security. He has also published more than 15 research articles in peer- reviewed international journals.
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Siva Janakiraman received his B.E. Degree from Bharathidasan University, Tiruchirapalli, India in 2003. He received M.Tech. Degree in Embedded Systems and Ph.D. Degree from SASTRA University, Thanjavur, India in 2007 and 2017 respectively. He is currently working as an Assistant Professor in the School of EEE, SASTRA University. His research interests include embedded system and information security. He has also published more than 15 research articles in peer- reviewed international journals.
K. Thenmozhi obtained a Ph.D. Degree from SASTRA University in 2008. Currently, she is working as Associate Dean in School of Electrical and Electronics Engineering at ASTRA University. Her research interest includes Networking and Wireless Communication. She received EDI award from broadcast Engineering Society for the year 2007. She has also published more than 80 research articles in various peer-reviewed international journals.
John Bosco Balaguru Rayappan received his M.Sc. and Ph.D. Degrees in Physics from Bharathidasan University, Tiruchirapalli, India in 1996 and 2003, respectively. He is currently working as a professor in the School of Electrical & Electronics Engineering, SASTRA University, Thanjavur, India. His current research interests include embedded systems, steganography, lattice dynamics, gas / chemical and biosensors and functional nanomaterials He has patented a novel embedding scheme which has been issued by USPTO during March 2015. He has also published more than 200 research articles in various peer-reviewed international journals.
Rengarajan Amirtharajan received his B.E. Degree from P.S.G. College of Technology, Bharathiyar University, Coimbatore, India in 1997. He received M.Tech. and Ph.D. Degrees from SASTRA University, Thanjavur, India in 2007 and 2012, respectively. He is currently working as an Associate Professor in the School of EEE, SASTRA University. His research interests include image processing, information hiding and information security. He has patented a novel embedding scheme which has been issued by USPTO during March 2015.He has also published more than 125 research articles in National & International journals.