Efficient test vector volume reduction based on equal run length coding technique

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Abstract

Excessive test power utilization is one of the major obstacles which the chip industry is facing at present. In SOC plan, test data volume is reduced extensively by using Test data compression strategies. In this paper, a variable-to-variable length compression method in light of encoding with perfect examples is presented. Initially, the don't care bits in the test vector are loaded with a proposed X -filling algorithm which is then encoded using the proposed Modified Equal Run Length Coding (MERLC) based encoding scheme. In relationship with the proposed X-filling and encoding scheme, an efficient decoder is designed and implemented with low area overhead. To assess the effectiveness of the proposed approach, it is tested on the ISCAS89 benchmark circuits. The tests results demonstrate that the proposed algorithm gets a higher compression ratio, when compared with the existing schemes. The Percentage compression of this scheme is 4.28%, 8.72%, 2.19%, 14.42% and 1.15% higher than those of ERLC, FDR, EFDR, Golomb and 9C coding respectively.

Introduction

Testing of Integrated Chips (ICs) becomes more and more difficult due to functional complexity and its size, caused by increase in integration levels of Very Large Scale Integrated (VLSI) chips. Testing of chips accounts for dominant cost factor in VLSI industry and reducing the cost of testing is the major challenge, VLSI designers and IC manufacturers are given to accomplish vivaciously. Test data volume and Test power are the two most important sources of test cost. By and large, much power is needed for a circuit when it undergoes test mode than in normal mode. This powerful utilization amid testing influences the circuit dependability [1]. Test force relies upon the quantity of sweep components present in the circuit. Productive test volume reduction procedures can reduce the test time, test power, and Automatic Test Equipment (ATE) memory requirement.

BuiltIn Self-test (BIST) is generally known as an important method for testing specific centers. It installs the precomputed test vectors in longer pseudorandom arrangements which are created on chip. The strategies' downside is their long test application time and is hard to accomplish high fault coverage. Alternate solution is compressing test set, reduces the test data volume and thereby the application time without applying futile test data to the Design under Test (DUT). One attractive methodology is to utilize Linear Feedback Shift Register (LFSR) reseeding. A few routines based on reseeding have been advanced and some commercial tools have been created for LFSR reseeding. LFSR reseeding exploit the run on the typical test vectors, that have very few specified bits and the compression ratio achieved using this method has direct relationship with the number of don't care bits/unspecified bits (X-bits)in test patterns. On the other hand, the LFSR method is not proficient when the number of specified bits is substantial in every test vector. To tackle the problem, different compression methods have been proposed for encoding source test data.

Linear compression schemes are exceptionally proficient at exploiting unspecified bits in the test cubes to accomplish a lot of compression. Coding schemes are categorized into five types based on code word size in the compressed test data [2], [3]: fixed-to-fixed length coding such as dictionary based coding [4] and LFSR-based reseeding coding [5], fixed to-variable-length such as Huffman-based coding [6], variable-to-fixed length such as traditional run-length based coding [7], variable-length coding such as VIHC coding [8], Golomb coding [9], Frequency Directed Run-length (FDR) coding [10], alternating run-length coding [11], [12], Extended Frequency-Directed Run-length (EFDR) coding [13], v9C coding [14], and (BMUC) coding [15] and finally the mixed coding in view of fixed and variable length such as VTFPVL [3].

In this paper, we have proposed a new modified compression technique not only to accomplish high compression ratio, also to achieve low average scan in and scan out test power with little hardware overhead. To achieve this, we exhibit a modified encoding technique based on equal run-length coding [16], [17], [18], [19], [20]. Our modified encoding scheme exploits the properties of a recently proposed test vector rearrangement algorithm [19], [20] to upgrade the compression ratio. To begin with, the test set with unspecified bits is X-filled and is further encoded with our modified equal run-length scheme. We additionally introduce the decompression architecture to translate the encoded test which will have little area overhead. The hardware portion of our module is coded in Verilog and this module is implemented on Xilinx Virtex4 XC4VLX200-11FF1513 FPGA. For performance comparison we use the MATLAB programming and the outcomes are contrasted with the comparable existing techniques.

The Section 2 discuss about some of the recent researches done with the objective of test data compression. Section 3 explains the proposed method along with its advantages. Section 4 describes the architecture of proposed compression technique and simple decompression architecture. The experimental results and comparison with other similar compression techniques are shown in Section 5. Finally, Section 6 concludes this paper.

Section snippets

Related work

Zhan and El-Maleh [19] proposed a scheme of test data compression taking into account run-length, to be specific equal-run-length coding (ERLC). Here they considered both runs of 0’s and 1’s and also explores the relationship between two consecutive runs in terms of its length. A shorter code word is used to encode the entire second consecutive runs with equal run length. They have also proposed a new scheme for filling the don't care bits, to maximize the number of consecutive equal length

Proposed method

It is known that 95–98% of the bits in the test cube generated by an ATPG for the purpose of testing any industrial circuit are unspecified bits. These bits can be uninhibitedly loaded with the logic values 0 or 1 keeping in mind the end goal is to decrease the volume of test data and/or the test power. The existing schemes discussed so far, effectively compressed the test data without exploring the relationship between consecutive runs. Therefore by considering the relationship between

Block schematic of the proposed method

This section describes the details for implementing the compression and decompression blocks of the proposed schematic as shown in Fig. 1.

The overall proposed structure includes a software part for compressing and the hardware part for decompressing the test vectors. In general the test vectors for different circuits are generated by the ATPG, and then these test vectors are fed to software based compression module to generate the compressed test data. The compressed test data are then

Results and discussion

In this segment, the viability of the proposed Modified ERLC scheme is verified on the ISCAS89 benchmark circuits. For examination with different plans, we make use of the Min-Test test sets, which are the same as [19], [20], [21], [22], [23], [24], [25], [26].

Conclusion

In order to enhance the test data volume reduction and thereby contributing in the overall test power reduction a modified technique based on ERLC compression scheme is presented in this paper. The main advantage of the proposed scheme includes an advanced X-filling scheme, a modified compression scheme that exploits this X-filling scheme and generates code words with less bit length, when compared to the existing compression techniques. Hardware architecture for decoder is designed and

Conflict of Interest

There is no conflict of interest.

V. Suresh Kumar is working as Assistant Professor in SRM Valliammai Engineering college, Chennai. He is doing his research in Anna University, Chennai. He completed his B.E. (EIE) from University of Madras and M.Tech. (VLSI Design) from Sathyabhama University, Chennai. He has over 17 years of experience in Teaching and Industrial Experience. He is Life member of ISTE and member of IEEE, IE(I) and ISC.

References (27)

  • A. Chandra et al.

    System-on-a-chip test data compression and decompression architectures based on Golomb codes

    IEEE Trans. Comput. Aided Des. Integr. Cir. Syst.

    (2001)
  • A. Chandra et al.

    Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes

    IEEE Trans. Comput.

    (2003)
  • A. Chandra et al.

    Reduction of SOC test data volume, scan power and testing time using alternating run-length codes

  • Cited by (1)

    V. Suresh Kumar is working as Assistant Professor in SRM Valliammai Engineering college, Chennai. He is doing his research in Anna University, Chennai. He completed his B.E. (EIE) from University of Madras and M.Tech. (VLSI Design) from Sathyabhama University, Chennai. He has over 17 years of experience in Teaching and Industrial Experience. He is Life member of ISTE and member of IEEE, IE(I) and ISC.

    R. Manimegalai is working as Professor in the Department of Information technology, has done Ph.D. in the Department of Computer Science and Engineering at IIT Madras. She received her B.E. (CSE) from PSG Tech., Coimbatore, and M.E. (CSE) from College of Engineering Guindy, Anna University. She has worked as software engineer with DCM Technologies, New Delhi and Team Lead in Xilinx Technologies, Hyderabad. She has served in various educational institutions, with different capacities, as Dean, Director and Principal She holds membership as Fellow in Institution of Engineers India (IEI), Senior Member in Computer Society of India (CSI), ISTE, IEEE, ACM and VLSI society of India. Her areas of interest include Security in Distributed, Embedded and IoT Systems, VLSI/FPGA Algorithms. She has widely published in journals and conferences and is guiding several PhD research scholars through Anna University, Chennai.

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