Elsevier

Microprocessors and Microsystems

Volume 69, September 2019, Pages 118-137
Microprocessors and Microsystems

Design and simulation of priority based dual port memory in quantum dot cellular automata

https://doi.org/10.1016/j.micpro.2019.06.004Get rights and content

Abstract

Design of dual port memory in QCA is an interesting field of study due to concurrent access of data from different ports, although the solution of the data conflict is a changeling task. However, Dual port memory design in QCA is reported in this paper. The architecture is based on the data priority. Priorities of the two ports are generated from the control logic block. Priority bit is required for conditions when the same memory location is requested by both of the ports and at least one operation is the write operation. The functionality of dual port memory is realized with concurrent access of memory array with parallel input-output data lines. Read–Write, Write–Write conflicts are resolved with a priority bit. Priority is uniquely calculated only when both the port request for same memory location access, i.e., the request for concurrent Read–Write or Write–Write operation. When the same memory location is selected, only the signal of the prior port is allowed and of other port is discarded. While the read operation is requested for both the port at same or different memory locations, have no data conflicts and both the ports are allowed to perform read operation. In the proposed architecture, to overcome data conflicts signals of the port having less priority are totally discarded. Significant results of Priority-based 4 × 4 dual port memory are depicted in terms of area and delay. The area, delay, and energy dissipation of Dual port QCA SRAM macro cell are 0.61 µm2, 2.0 clock cycles, and 393.9 meV, respectively. A comparative study of the proposed dual port memory in QCA, single port memory in QCA and dual port memory in CMOS are also performed in this work. The result explored that proposed dual port memory proportionately efficient with respect to the QCA single port memory as well as CMOS dual port memory in terms of area-delay-energy.

Introduction

After a magnificent enhancement of silicon technology, now is suffering due to its high power dissipation, leakage of current and physical designing limits. Quantum dot cellular automata (QCA) has arrived as a significant research domain in the Nano-scale computation domain [1], [2], [3], [4]. Since from its commencement in 1993 by Lent et al. [2], and after decades of exhaustive research on QCA, now it is proved to be a sturdy alternative to CMOS technology. After experimental verification in 1997 [3], the QCA technology emerges as a low power, high device density and a THz processing speed in Nanotechnology. With high-speed switching capabilities, QCA layouts are an arrangement of cells those are operated by the Columbic interactions. One major advantage of QCA is that it acts on the polarization [2], [5], [6], [7], [8], [9], [10] of cells rather than the transmission of current through devices, thus minimizing the demand of energy for operations. As an alternative of interconnections through wires, the electrostatic influence on the neighbor cells is the key for information transfer as well, in case of the paradigm in QCA. In this research work, an attempt is made to design conflict resolvable dual port memory design and implementation in QCA technology. The main difference between dual port memory and single port memory, as single port memory can only access at one address at a time. Therefore, a single port memory allows only one memory cell can be read/write during each clock cycles, whereas in dual port memory, two memory cell can read/write during each clock cycles. Dual port memory is implemented in CMOS technology. Most recent computer CPU implements its processor registers as dual ported or multi-ported. Video RAM (VRAM) is a type of CMOS RAM which uses dual port memory [11], [12]. Design of Multiprocessor computer architecture in QCA, the dual port memory will act as an interconnection network between two processors. Dual port or multi-port SRAM memory design will lead to the design of shared memory architecture. Reordering the sequence of memory access request technique is proposed in CMOS technology to avoid the data conflict problem [11]. Memory access can be configured with multiple memory banks system is also reported in CMOS Technology [12].

The first attempt is made to design and simulate the architecture of dual port memory in QCA literature. Proposed dual port SRAM macro cell comprises of a memory cell and with peripheral circuits. The peripheral circuit is consisting of a priority bit, one read/write input signal, one word line and a bit line for each port. The functionality of dual port memory is realized with concurrent access of memory array with parallel input-output data lines. Read–Write, Write–Write conflicts are resolved with a priority bit. Priority is uniquely calculated only when both the port request for same memory location access, i.e., concurrent Read–Write, concurrent Write–Write operation request. In terms of area-delay-energy, it is shown that proposed dual port memory proportionately efficient with respect to the QCA single port memory as well as CMOS dual port memory.

The rest of the paper is organized as follows. In Section 2, the basic idea of QCA cell is discussed. A brief description of Dual port memory and some relevant work in QCA domain are illustrated at Sections 3 and 4 respectively. Proposed works are presented in Section 5. The result and discussions are demonstrated in Section 6 with corresponding comparative studies. Finally the conclusion of this article is portrayed in Section 7.

Section snippets

QCA basics

Quantum dots are 3-Dimensional quantization of a bulk molecule structure. Conceptually, QCA cell is consisting of four quantum dots situated at four different corners of a square [1], [13], [14], [15] and two extra electrons are confining within a cell which in turn reside diagonally apart from each other at a maximum distance because of Columbic repulsion. The outer substrate of the cell is layered by the material with a higher band gap than that of the inner one. This ensures that the free

Dual port SRAM

Dual port SRAM consists of two independent portssingle bond A and B. Data can be written to either port or both of the SRAM and can also read from either or both port of the SRAM concurrently at different addresses. Therefore, single port SRAM allows only one memory cell to read/write during each clock cycles. In dual port memory, each of the port has its own data in, address lines; write enable and data out as shown in Fig. 5.

Dual port memory allows the user to perform both read and write operations on

Related work

In QCA, several architectures of single port memory, 3-bit synchronous counter are proposed and implemented in [23], [24], [25], [26], [27], [28]. In this article, QCA based memory cells are implemented, different architectures for memory and how different operations are done in memory are discussed and implemented. In QCA technology, there is no such research work is found to design and implement a dual port memory architecture. In Section 4.1, the review work on single port SRAM memory cell

Proposed priority based dual port memory architecture using QCA

In dual port memory, user can access two memory locations at a time as discussed in Section 3. However, if same memory location is accessed at a time and at least one operation is write operation then data conflict is occurred. To remove the conflict, we can stall signal of one port for some delay. Nevertheless, if we try to stall the signal of one port, it may use infinite number of buffers in QCA because of two signals come simultaneously and signal can't be stalled for some delay. For these

Result and discussion

Each block and the entire architecture are designed using QCADesigner tool of version 2.0.3 [33]. The coherence vector simulation engine is used for simulation of proposed QCA circuit. The parameters of coherence vector simulation engine are listed below. The cell size is 18 nm × 18 nm and quantum dot size is 5 nm. The number of sample for simulation is considered 12,800. The accuracy of simulation depends on this number of tested or sample data. The working temperature is 1.0 K. Relaxation

Conclusion

QCA based dual port memory is proposed in this article. This architecture is based on the priority and the circuit is synchronized. Priorities of two ports are generated from control logic block. The proposed architecture resolves the data conflicts problem by discarding, the priority signal of the port having less priority. The operation of dual port memory is realized with concurrent access of memory array with Parallel input-output data lines. Read–Write, Write–Write conflicts are resolved

Conflict of interest

None.

Acknowledgment

The authors are grateful to The Science & Engineering Research Board (DST-SERB), Govt. of. India, for providing with the grant for accomplishment of the project under the Project File No. ECR/2016/000613.

Kunal Das received the B. Tech (Information Technology) and M. Tech (Information Technology) from Calcutta University, Kolkata, India. He was awarded the Ph.D degree from University of Kalyani. He is working as Associate professor in Department of Computer Science and Engineering, Narula Institute of Technology, Agarpara, Kolkata, India. He is former Assistant Professor in the Department of Computer Science & Engineering, National Institute of Technology, Arunachal Pradesh, India. He is the

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    Kunal Das received the B. Tech (Information Technology) and M. Tech (Information Technology) from Calcutta University, Kolkata, India. He was awarded the Ph.D degree from University of Kalyani. He is working as Associate professor in Department of Computer Science and Engineering, Narula Institute of Technology, Agarpara, Kolkata, India. He is former Assistant Professor in the Department of Computer Science & Engineering, National Institute of Technology, Arunachal Pradesh, India. He is the recipient of DST-SERB Early Carrier Research Award (FILE NO. ECR/2016/000613) under which this research work is completed. He has authored several Int. journals papers and several conference papers and reviewer of many SCI journals like Elsevier Microelectronics journal, Springer JETTA, IEEE Trans. and many international conferences. His research interests includes Nano devices like Quantum dot Cellular Automata, CNTFET, TFET, VLSI, Digital Microfludic BioChip, Computer architectures, and hardware.

    Arindam Sadhu received M.tech in VLSI design from WBUT, West Bengal, India. He is working as Junior Research Fellow under DST-SERB research project (FILE NO. ECR/2016/000613) and currently working towards his PhD work. His research interest includes Quantum dot Cellular Automata, VLSI design.

    Debashis De received M. Tech degree from University of Calcutta in 2002. He obtained his Ph.D (Engineering) from Jadavpur University in 2005. He is the senior member of IEEE and member of International Union of Radio science. He worked as R & D Engineer of Telektronics. Presently he is working as Head of the Department and Associate Professor in the Department of Computer Science and Engineering of West Bengal University of Technology, India and Adjunct Research Fellow of University of Western Australia, Australia. He was awarded the prestigious Boyscast Fellowship by the Department of Science and Technology, Govt. of India to work at the Herriot-Watt University, Scotland, UK. He received the Endeavour Fellowship Award during 2008–2009 by DEST Australia to work in the University of Western Australia. He also received the Young Scientist award both in 2005 at New Delhi and in 2011 at Istanbul, Turkey from International Union of Radio Science, Head Quarter, Belgium. His research interest includes location and handoff management, mobile cloud computing, traffic forecasting, green mobile networks and low power Nano device designing for mobile application. He has published more than sixty peer reviewed international journals, fifty conference papers, two research monographs and ten books.

    Jadav Chandra Das received his MTech degree in multimedia and software systems from WBUT, West Bengal, India, in 2011. Presently, he is an assistant professor in the Department of Computer Science and Engineering, Swami Vivekananda Institute of Science and Technology under WBUT, Kolkata, India. His research interest includes cryptography, QCA-based image processing, and reversible logic circuit design.

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